Aaron D Ng

US Patent:

7840919, Nov 23, 2010

Filed:

Feb 1, 2008

Appl. No.:

12/024343

Inventors:

Qiang Wang - Campbell CA, US
Aaron Ng - Belmont CA, US
Rajat Aggarwal - Sunnyale CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 2, 716 13, 716 14, 716 16

Abstract:

The availability of device resources of an IC are quantified for a circuit design by building a representation of resource sites for the IC. Initial availability values are assigned to the resource sites, and any components having locking constraints are identified and placed into their respective sites. From the remaining resource sites, candidate sites for a component of the circuit design are identified. The candidate sites are summed, and the initial availability values of the candidate sites are modified according to the sum.

US Patent:

20190114499, Apr 18, 2019

Filed:

Oct 17, 2017

Appl. No.:

15/786267

Inventors:

- San Jose CA, US
Ashish Sirasao - San Jose CA, US
Aaron Ng - San Jose CA, US
Yongjun Wu - Cupertino CA, US
Jindrich Zejda - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06K 9/00
G06F 3/06
G06K 9/46
G06T 1/60
G06T 1/20

Abstract:

An example preprocessor circuit for formatting image data into a plurality of streams of image samples includes: a first buffer configured to store a plurality of rows of the image data and output a row of the plurality of rows; a second buffer, coupled to the first buffer, including a plurality of storage locations to store a respective plurality of image samples of the row output by the first buffer; a plurality of shift registers; an interconnect network including a plurality of connections, each connection coupling a respective one of the plurality of shift registers to more than one of the plurality of storage locations, one or more of the plurality of storage locations being coupled to more than one of the plurality of connections; and a control circuit configured to load the plurality of shift registers with the plurality of image samples based on the plurality of connections and shift the plurality of shift registers to output the plurality of streams of image samples.

US Patent:

20190114534, Apr 18, 2019

Filed:

Oct 17, 2017

Appl. No.:

15/785685

Inventors:

- San Jose CA, US
Aaron Ng - San Jose CA, US
Ashish Sirasao - San Jose CA, US
Elliott Delaye - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06N 3/063
G06N 3/08
G06N 3/04

Abstract:

At least one neural network accelerator performs operations of a first subset of layers of a neural network on an input data set, generates an intermediate data set, and stores the intermediate data set in a shared memory queue in a shared memory. A first processor element of a host computer system provides input data to the neural network accelerator and signals the neural network accelerator to perform the operations of the first subset of layers of the neural network on the input data set. A second processor element of the host computer system reads the intermediate data set from the shared memory queue, performs operations of a second subset of layers of the neural network on the intermediate data set, and generates an output data set while the neural network accelerator is performing the operations of the first subset of layers of the neural network on another input data set.