Aaron B Rogers

US Patent:

7567135, Jul 28, 2009

Filed:

Nov 30, 2007

Appl. No.:

11/947919

Inventors:

Aaron S. Rogers - Pflugerville TX, US
Daniel W. Bailey - Austin TX, US
Roger D. Pannell - Brookline NH, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03B 5/08
H03B 5/12

US Classification:

331 48, 331173

Abstract:

To determine performance degradation at functional module in a normal power state due to a power control device, voltages are applied to oscillators at a power diagnostic module. A first voltage is a supply voltage for the data processing device, and a second voltage is a supply voltage applied at a functional module of the data processing device. Counters are adjusted based on the oscillators to determine the oscillators' respective frequencies. In addition, the power diagnostic module can include a timer to measure the length of time that the functional module is in a low-power state, and an analog to digital converter to measure the voltage applied to the functional module during transitions to and from the low-power state.

US Patent:

8369133, Feb 5, 2013

Filed:

Aug 24, 2010

Appl. No.:

12/862131

Inventors:

Aswin K. Gunasekar - Austin TX, US
Daniel W. Bailey - Austin TX, US
Aaron S. Rogers - Pflugerville TX, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G11C 7/10

US Classification:

365154, 36518905

Abstract:

A method, electronic device, and system are provided in which data is stored in a gateable retention storage element. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus which includes a silicon chip. The method includes storing a data value in a storage element, wherein the storage element is at least one of a flip-flop, a latch or a register. The method also includes placing the storage element in a low power state comprising removing one or more existing connections between the actual ground node and at least one other component in the storage element. The method also includes maintaining the data value in the storage element subsequent to placing the storage element into the low power state. The electronic device includes a storage component for storing a data value. The electronic device also includes a pair of cross-coupled inverter components communicatively coupled to the storage component, the pair of cross-coupled inverter components being adapted to maintain the data value stored by the storage component subsequent to placing the storage component into a low power state and being adapted to maintain a connection with an actual ground node subsequent to placing the storage component into the low power state.

US Patent:

8415972, Apr 9, 2013

Filed:

Nov 17, 2010

Appl. No.:

12/948596

Inventors:

Aaron S. Rogers - Pflugerville TX, US
Daniel W. Bailey - Austin TX, US
Eric Quinnell - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H03K 17/16

US Classification:

326 34

Abstract:

A semiconductor device includes a primary voltage rail, a secondary voltage rail, a plurality of transistors coupled between the primary and secondary voltage rails, and control logic operable to enable a first subset of the plurality of transistors to couple the primary voltage rail to the secondary voltage rail. During a steady state condition, the first subset comprises less than all of the plurality of transistors.

US Patent:

20050093577, May 5, 2005

Filed:

Nov 4, 2003

Appl. No.:

10/701667

Inventors:

Liem Nguyen - Austin TX, US
Xiaojie He - Austin TX, US
Brian Gaide - Austin TX, US
Kerry Ilgenstein - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Claudia Stanley - Austin TX, US
Aaron Rogers - Austin TX, US
Zheng Chen - Macungie PA, US

International Classification:

H03K019/094

US Classification:

326105000

Abstract:

Multiplexer circuits are disclosed, such as for example for programmable logic devices. As an example of one embodiment, a multiplexer circuit is disclosed having a default state and a state-locking latch.

US Patent:

20130009697, Jan 10, 2013

Filed:

Jul 6, 2011

Appl. No.:

13/176842

Inventors:

Daniel W. Bailey - Austin TX, US
Aaron S. Rogers - Pflugerville TX, US
James J. Montanaro - Austin TX, US
Bradley G. Burgess - Austin TX, US
Peter J. Hannan - Austin TX, US

International Classification:

G05F 3/02

US Classification:

327544

Abstract:

Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.