Adam Ray Duncan

US Patent:

20190348986, Nov 14, 2019

Filed:

Jul 24, 2019

Appl. No.:

16/520591

Inventors:

- Crane IN, US
Matthew John Gadladge - Bloomington IN, US
Adam Ray Duncan - Bloomington IN, US
Brett J. Hamilton - Heltonville IN, US
Andrew Mark Howard - Bloomington IN, US

Assignee:

The United States of America, as represented by the Secretary of the Navy - Arlington VA

International Classification:

H03K 19/177
G11C 11/16
G11C 17/16

Abstract:

Various embodiments include providing a MTJ-based LUT and adding a system that short circuits or causes dielectric layer breakdown of selected MTJ junctions to permanently finalize a desired logic state configuration of selected MTJs that is read out by the LUT. Additional embodiments disable dielectric layer breakdown or short circuit control circuits to prevent further alterations to MTJ that have not had their dielectric layers broken down or shorted out. A control system then alters reading out the MTJ-based LUT to sense original higher and lower resistance values of un-shorted/altered MTJs as a higher resistance state and a shorted or dielectric layer that has been broken down as a lower resistance state. This combines the flexibility of a multiple-time programmable LUT-based FPGA with the security and reliability of a one-time programmable LUT-based FPGA which has characteristics of a fixed logic non-programmable integrated circuit or application specific integrated circuit (ASIC).

US Patent:

20190222202, Jul 18, 2019

Filed:

Dec 28, 2018

Appl. No.:

16/235228

Inventors:

- Crane IN, US
Adam Duncan - Bloomington IN, US
Matthew Gadlage - Bloomington IN, US
Austin Roach - Bloomington IN, US
Glenn Burger - Bloomington IN, US

International Classification:

H03K 3/03
G01T 1/24

Abstract:

Apparatuses and methods using current-starved ring oscillator biased by floating gate transistors with a variety of applications including as a power-free radiation detector or silicon age determination or odometer system.

US Patent:

20180301427, Oct 18, 2018

Filed:

Apr 12, 2018

Appl. No.:

15/951576

Inventors:

- Crane IN, US
Matthew Gadlage - Bloomington IN, US
Adam Duncan - Bloomington IN, US
Brett Hamilton - Heltonville IN, US
Brett Werner - Jasper IN, US
Austin Roach - Bloomfield IN, US

Assignee:

The United States of America, as represented by the Secretary of the Navy - Crane IN

International Classification:

H01L 23/00

Abstract:

Exemplary systems and methods for inhibiting backend access to an integrated circuit are provided including latch-up circuits triggered by photons, electrons, and ions to create catastrophic failures in integrated circuits. Exemplary systems include latch-up circuits with floating gate bit cells which, when triggered, close the latch-up circuits so that the latch-up circuits can amplify current in a positive feedback loop to create a short circuit to inhibit unauthorized individuals from probing or modifying an integrated circuit.

US Patent:

20170140832, May 18, 2017

Filed:

Jan 27, 2017

Appl. No.:

15/417660

Inventors:

- Crane IN, US
James David Ingalls - Bedford IN, US
Matthew Gadlage - Bloomington IN, US
Adam Duncan - Bloomington IN, US
Andrew Howard - Bloomington IN, US

International Classification:

G11C 16/34
G11C 16/04
G11C 16/10
G11C 16/26

Abstract:

A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.

US Patent:

20170103818, Apr 13, 2017

Filed:

Jul 11, 2016

Appl. No.:

15/206904

Inventors:

- Crane IN, US
Matthew Gadlage - Bloomington IN, US
Adam Duncan - Bloomington IN, US
James David Ingalls - Bedford IN, US
Matthew Kay - Jasper IN, US

International Classification:

G11C 29/12
G11C 16/14

Abstract:

Apparatuses and methods are provided using a plurality of interrupted IC operations to detect various conditions or changes of interest to integrated circuit (IC) elements (e.g., memory cells of NAND Flash memories or floating gate transistor) such as program/erase stress, total ionizing dose, and heavy ion exposure which modify normal IC element bit state changes. An exemplary method can include controlling a plurality of selected IC elements to execute a series of PROGRAM or ERASE operations on all of the plurality of selected elements that are each interrupted or halted before a normal or first time period required for the PROGRAM or ERASE operation has elapsed. An exemplary system records a number of interrupted operations required to cause a state change in each of the plurality of selected IC elements. Embodiments of the invention enable detection of stresses far below at least some thresholds for IC element or bit cell failure.

US Patent:

20160284418, Sep 29, 2016

Filed:

Jun 6, 2016

Appl. No.:

15/174022

Inventors:

- Crane IN, US
James David Ingalls - Bedford IN, US
Matthew Gadlage - Bloomington IN, US
Adam Duncan - Bloomington IN, US
Andrew Howard - Bloomington IN, US

International Classification:

G11C 16/34
G11C 16/10
G11C 16/26
G11C 16/04

Abstract:

A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.

US Patent:

20160276339, Sep 22, 2016

Filed:

Mar 25, 2015

Appl. No.:

14/668081

Inventors:

- Crane IN, US
Mark Savage - Bloomington IN, US
Patrick L. Cole - Bedford IN, US
Adam R. Duncan - Bloomington IN, US

International Classification:

H01L 27/07
H03K 17/693

Abstract:

Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using a combination of a metal-oxide semiconductor field effect transistor (MOSFET) and junction field effect transistor (JFET) disposed perpendicularly and within a certain orientation to each other. An embodiment of the invention can be formed and operable for modulating current and/or voltage response or mitigating electromagnetic or radiation interference effects on the MOSFET by controlling a semi-conductive channel region (SCR) using an additional gate, e.g., JFET, disposed perpendicularly with respect to the MOSFET configured to generate an electromagnetic field into the MOSFET's semi-SCR. A control system for controlling operation is also provided to include automated systems including sensors as well as manually operated systems. Automated systems can include radiation sensors as well as other control systems such as radio frequency transmitter or receiver systems. Methods of operation for a variety of modes are also provided.

US Patent:

20160258999, Sep 8, 2016

Filed:

May 17, 2016

Appl. No.:

15/156807

Inventors:

- Crane IN, US
Adam Duncan - Bloomington IN, US

International Classification:

G01R 31/303
G01R 31/302
G06F 13/42
G01R 31/317
G06F 13/36
G06F 13/40

Abstract:

A highly flexible, compact, lightweight, and portable testing system for use with radiation testing activities. The testing system is coupled to a device under test (DUT), which can be positioned in such a way that the top of the die package is exposed to the direct ion beam during radiation testing. A variety of sensors, onboard memory systems, programmable interfaces, onboard control systems, data output devices, and different types of interfaces are also provided which provide an ability to perform testing procedures while having a maximum ability to orient the DUT and perform a wide variety of testing currently unavailable.