Adam R Duncan

US Patent:

20160211021, Jul 21, 2016

Filed:

Mar 29, 2016

Appl. No.:

15/083544

Inventors:

- Crane IN, US
Matthew Kay - Jasper IN, US
James D. Ingalls - Bedford IN, US
Adam Duncan - Bloomington IN, US
Austin Roach - Bloomfield IN, US

International Classification:

G11C 16/04
G11C 16/06

Abstract:

An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus are provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.

US Patent:

20150144695, May 28, 2015

Filed:

Apr 7, 2014

Appl. No.:

14/246173

Inventors:

- Crane IN, US
Matthew Kay - Jasper IN, US
James D. Ingalls - Bedford IN, US
Adam Duncan - Bloomington IN, US
Austin Roach - Bloomfield IN, US

Assignee:

The United States of America as represented by the Secretary of the Navy - Crane IN

International Classification:

G06K 19/077
G06K 7/00
H01L 21/265
H01L 27/115
H01L 29/66

US Classification:

235441, 257316, 438258

Abstract:

An irreproducible and re-emergent unique structure or pattern identifier manufacturing and detection method, system, and apparatus is provided. A non-volatile floating gate charge storage device can include a block of floating gate transistors that can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitrite-oxide region, and a control gate region. A structure altering stress effect is applied to the block of transistors to create a passage region in a random number of floating gate regions of floating gate transistors which changes charge storage or electrical characteristics of random elements of the block of transistors. The passage region alters charges on a floating gate region to escape in a different manner than pre-alteration form causing the floating gate region to lose its charge. An apparatus for recording and detecting such differences in pre and post alteration can also be provided.

US Patent:

20140330533, Nov 6, 2014

Filed:

Jun 3, 2013

Appl. No.:

13/908470

Inventors:

Matthew Gadlage - Jasper IN, US
Adam Duncan - Bloomington IN, US

International Classification:

G01R 31/317

US Classification:

702120

Abstract:

A highly flexible, compact, lightweight, and portable testing system for use with radiation testing activities. The testing system is coupled to a device under test (DUT), which can be positioned in such a way that the top of the die package is exposed to the direct ion beam during radiation testing. A variety of sensors, onboard memory systems, programmable interfaces, onboard control systems, data output devices, and different types of interfaces are also provided which provide an ability to perform testing procedures while having a maximum ability to orient the DUT and perform a wide variety of testing currently unavailable.