Adrian Robert Pearson

US Patent:

8630354, Jan 14, 2014

Filed:

Jun 16, 2006

Appl. No.:

11/454410

Inventors:

Musa Jahanghir - Palo Alto CA, US
Adrian R. Pearson - Phoenix AZ, US
Prasenjit Biswas - Saratoga CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04N 7/12

US Classification:

37524026, 37524001

Abstract:

Apparatus, systems and methods for hardware accelerated compressed video bitstream escape code handling are disclosed including an apparatus comprising a bitstream parser (BSP) to parse a bitstream of compressed video data. The BSP includes circuitry to extract uncompressed run and level data from the bitstream when the BSP detects an escape code in the bitstream. Other implementations are disclosed.

US Patent:

8645677, Feb 4, 2014

Filed:

Sep 28, 2011

Appl. No.:

13/247042

Inventors:

Hormuzd M. Khosravi - Portland OR, US
Peter R. Munguia - Chandler AZ, US
Adrian R. Pearson - Hillsboro OR, US
Steve J. Brown - Chandler AZ, US
David A. Schollmeyer - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 21/00

US Classification:

713150, 713182

Abstract:

An embodiment uses hardware secrets secured within a security engine to provide a secure solution for field key provisioning. An embodiment is operating system independent due to the out-of-band communications with the security engine. Secrets need not be provisioned during manufacturing time. An embodiment may ensure only security engine specific provisioned secrets are used at runtime. Other embodiments are addressed herein.

US Patent:

20060149877, Jul 6, 2006

Filed:

Jan 3, 2005

Appl. No.:

11/028405

Inventors:

Adrian Pearson - Phoenix AZ, US

International Classification:

G06F 13/24

US Classification:

710260000

Abstract:

A method includes receiving a first interrupt from a digital media processor and blocking execution of an application program while the first interrupt is being handled. The method further includes receiving a second interrupt from the digital media processor and allowing execution of the application program to continue while the second interrupt is being handled.

US Patent:

20060210189, Sep 21, 2006

Filed:

Mar 21, 2005

Appl. No.:

11/085943

Inventors:

Adrian Pearson - Phoenix AZ, US

International Classification:

G06K 9/40

US Classification:

382262000

Abstract:

A system, apparatus, method and article to filter media signals are described. The apparatus may include a media processor. The media processor may include an image signal processor having multiple processing elements to concurrently process a pixel matrix by executing single instruction stream, multiple data streams instructions to determine a matrix median pixel value, and replace a pixel value from said pixel matrix with said matrix median pixel value. Other embodiments are described and claimed.

US Patent:

20140082724, Mar 20, 2014

Filed:

Sep 14, 2012

Appl. No.:

13/976342

Inventors:

Adrian R. Pearson - Beaverton OR, US
Christopher Andrew Thornburg - Chandler AZ, US
Steven J. Brown - Phoenix AZ, US
Peter R. Munguia - Chandler AZ, US

International Classification:

G06F 21/57

US Classification:

726 22

Abstract:

A disclosed example method involves when transitioning a processor system to a low-power mode, generating at least a first signature based on a data structure storing memory addresses of memory regions to be protected during the low-power mode. During a resume process of the processor system from the low-power mode, at least a second signature is generated based on the data structure storing the memory addresses of the memory regions to be protected during the low-power mode. When the first signature matches the second signature, the processor system resumes from the low-power mode. When the first signature does not match the second signature, an error is generated.

US Patent:

20210264042, Aug 26, 2021

Filed:

Apr 22, 2021

Appl. No.:

17/237102

Inventors:

- Santa Clara CA, US
Lokpraveen B. Mosur - Gilbert AZ, US
Tony Hurson - Austin TX, US
Patrick Fleming - Laois, IE
Adrian R. Pearson - Beaverton OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

G06F 21/62
H04L 29/06
G06F 21/78
H04L 9/32
H04L 9/08

Abstract:

Various embodiments are generally directed to an apparatus, method and other techniques to determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.

US Patent:

20190266103, Aug 29, 2019

Filed:

May 8, 2019

Appl. No.:

16/406074

Inventors:

Adrian Robert Pearson - Beaverton OR, US
David Ray Noeldner - Fort Collins CO, US
Niels Juel Reimers - Folsom CA, US
Emily Po-Kay Chung - Cupertino CA, US
Gamil Assudan Cain - El Dorado Hills CA, US
Thomas Rodel Bowen - Hillsboro OR, US
Teddy Gordon Greer - Freemont CA, US
Jonathan Martin Hughes - Longmont CO, US

International Classification:

G06F 12/14
H04L 9/08
G06F 3/06

Abstract:

A self-encrypting drive (SED) comprises an SED controller and a nonvolatile storage medium (NVSM) responsive to the SED controller. The SED controller enables the SED to perform operations comprising: (a) receiving an encrypted media encryption key (eMEK) for a client; (b) decrypting the eMEK into an unencrypted media encryption key (MEK); (c) receiving a write request from the client, wherein the write request includes data to be stored and a key tag value associated with the MEK; (d) using the key tag value to select the MEK for the write request; (e) using the MEK for the write request to encrypt the data from the client; and (f) storing the encrypted data in a region of the NVSM allocated to the client. Other embodiments are described and claimed.

US Patent:

20190102568, Apr 4, 2019

Filed:

Sep 30, 2017

Appl. No.:

15/721769

Inventors:

- SANTA CLARA CA, US
LOKPRAVEEN B. MOSUR - Gilbert AZ, US
TONY HURSON - Austin TX, US
PATRICK FLEMING - Portlaoise, IE
ADRIAN R. PEARSON - Hillsboro OR, US

International Classification:

G06F 21/62
H04L 29/06

Abstract:

Various embodiments are generally directed to an apparatus, method and other techniques to de determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.