Akshay Arun Mote
age ~38
from Folsom, CA
- Also known as:
-
- Akshay A Mote
- Akshay C Mote
- Akshay M Mote
Akshay Mote Phones & Addresses
- Folsom, CA
- Sunnyvale, CA
- Los Angeles, CA
Work
-
Company:Intel corporationAug 2012
-
Address:Folsom, California
-
Position:Component design engineer
Education
-
Degree:M.S
-
School / High School:University of Southern California2010 to 2012
-
Specialities:Electrical Engineering
Skills
Vlsi • Cadence Virtuoso • Logic Design • Perl • Simulations • Verilog • Eda • C++ • Vhdl • Systemverilog • Computer Architecture • Rtl Design • Very Large Scale Integration • C • Functional Verification • Static Timing Analysis • Uvm • Asic • Field Programmable Gate Arrays • System on A Chip • Integrated Circuits • Microsoft Excel • Python • Low Power Design • Formal Verification • Rtl Verification • Rtl Coding • Cdc • Physical Design • Tcl • Synopsys Tools • Digital Design • Logic Synthesis • Vcs • Verdi • Universal Verification Methodology • Lint • Power Analysis • Low Power Design • Soc Design • Microarchitecture • Cpu Design • Gpu Design • Cache Coherency • Intersystems Cache • Dynamic Random Access Memory • Flash Memory • Memory Sub Systems • Solid State Drive • Matlab • Mixed Signal • Debugging • Circuit Design • Spice
Languages
English • Hindi • Marathi
Ranks
-
Certificate:Comprehensive System Verilog
Interests
Playing Table Tennis
Industries
Semiconductors
Us Patents
-
Fuseload Architecture For System-On-Chip Reconfiguration And Repurposing
view source -
US Patent:20210117374, Apr 22, 2021
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Filed:Nov 4, 2020
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Appl. No.:17/089121
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Inventors:- Boise ID, US
Praveen Gopalapuram - Folsom CA, US
Akshay Arun Mote - Sunnyvale CA, US -
International Classification:G06F 15/80
G06F 9/30 -
Abstract:Methods, systems, and devices that support fuseload architectures for system-on-chip (SoC) reconfiguration and repurposing are described. Trim data may be loaded from fuses to registers on a die based on a fuse header. For example, a set of registers coupled with a set of fuses on the die may be identified, where the set of fuses may store trim data to be copied to the registers as part of a fuseload procedure. In such cases, one or more fuse headers may be identified within the trim data, and each fuse header may correspond to a fuse group that includes a subset of fuses. Based on one or more subfields within a fuse header, a mapping between fuse addresses and register addresses may be determined, and the trim data from each fuse group may be copied into a set of registers based on the mapping.
-
Fuseload Architecture For System-On-Chip Reconfiguration And Repurposing
view source -
US Patent:20200050581, Feb 13, 2020
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Filed:Aug 13, 2018
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Appl. No.:16/102050
-
Inventors:- Boise ID, US
Praveen Gopalapuram - Folsom CA, US
Akshay Arun Mote - Sunnyvale CA, US -
International Classification:G06F 15/80
G06F 9/30 -
Abstract:Methods, systems, and devices that support fuseload architectures for system-on-chip (SoC) reconfiguration and repurposing are described. Trim data may be loaded from fuses to registers on a die based on a fuse header. For example, a set of registers coupled with a set of fuses on the die may be identified, where the set of fuses may store trim data to be copied to the registers as part of a fuseload procedure. In such cases, one or more fuse headers may be identified within the trim data, and each fuse header may correspond to a fuse group that includes a subset of fuses. Based on one or more subfields within a fuse header, a mapping between fuse addresses and register addresses may be determined, and the trim data from each fuse group may be copied into a set of registers based on the mapping.
Resumes
Senior Soc Design Engineer
view sourceLocation:
384 Chan Ct, Folsom, CA
Industry:
Semiconductors
Work:
Intel Corporation - Folsom, California since Aug 2012
Component Design Engineer
Intel Corporation - Folsom California Feb 2012 - May 2012
Graduate Technical Intern - Design Automation Engineer
University of Southern California Aug 2010 - May 2012
Graduate Student
Tata Consultancy Services Sep 2008 - Aug 2010
Asst. Systems Engineer
Component Design Engineer
Intel Corporation - Folsom California Feb 2012 - May 2012
Graduate Technical Intern - Design Automation Engineer
University of Southern California Aug 2010 - May 2012
Graduate Student
Tata Consultancy Services Sep 2008 - Aug 2010
Asst. Systems Engineer
Education:
University of Southern California 2010 - 2012
M.S, Electrical Engineering Walchand College of Engineering 2004 - 2008
B.E, Electronics Engineering
M.S, Electrical Engineering Walchand College of Engineering 2004 - 2008
B.E, Electronics Engineering
Skills:
Vlsi
Cadence Virtuoso
Logic Design
Perl
Simulations
Verilog
Eda
C++
Vhdl
Systemverilog
Computer Architecture
Rtl Design
Very Large Scale Integration
C
Functional Verification
Static Timing Analysis
Uvm
Asic
Field Programmable Gate Arrays
System on A Chip
Integrated Circuits
Microsoft Excel
Python
Low Power Design
Formal Verification
Rtl Verification
Rtl Coding
Cdc
Physical Design
Tcl
Synopsys Tools
Digital Design
Logic Synthesis
Vcs
Verdi
Universal Verification Methodology
Lint
Power Analysis
Low Power Design
Soc Design
Microarchitecture
Cpu Design
Gpu Design
Cache Coherency
Intersystems Cache
Dynamic Random Access Memory
Flash Memory
Memory Sub Systems
Solid State Drive
Matlab
Mixed Signal
Debugging
Circuit Design
Spice
Cadence Virtuoso
Logic Design
Perl
Simulations
Verilog
Eda
C++
Vhdl
Systemverilog
Computer Architecture
Rtl Design
Very Large Scale Integration
C
Functional Verification
Static Timing Analysis
Uvm
Asic
Field Programmable Gate Arrays
System on A Chip
Integrated Circuits
Microsoft Excel
Python
Low Power Design
Formal Verification
Rtl Verification
Rtl Coding
Cdc
Physical Design
Tcl
Synopsys Tools
Digital Design
Logic Synthesis
Vcs
Verdi
Universal Verification Methodology
Lint
Power Analysis
Low Power Design
Soc Design
Microarchitecture
Cpu Design
Gpu Design
Cache Coherency
Intersystems Cache
Dynamic Random Access Memory
Flash Memory
Memory Sub Systems
Solid State Drive
Matlab
Mixed Signal
Debugging
Circuit Design
Spice
Interests:
Playing Table Tennis
Languages:
English
Hindi
Marathi
Hindi
Marathi
Certifications:
Comprehensive System Verilog
Advanced System Verilog For Design
Advanced System Verilog For Design
Youtube
Googleplus
Akshay Mote
Lived:
Folsom, California, USA
Los Angeles, California, USA
Mumbai, India
Kolhapur, India
Sangli, India
Bangalore, India
Los Angeles, California, USA
Mumbai, India
Kolhapur, India
Sangli, India
Bangalore, India
Work:
Intel Corporation - Component Design Engineer (2012)
Education:
University of Southern California - MS EE (Vlsi Design)
About:
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Akshay Mote
Education:
Padmashree Dr D.Y.Patil University - Mechanical Engineering
About:
No one messes with me!!
Tagline:
Never say never again
Akshay Mote
Akshay Mote
Akshay Mote
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Akshay Mote
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Akshay Mote
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Akshay Mote
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Akshay Mote
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Akshay Mote
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Akshay Mote
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Akshay Mote
view sourceGet Report for Akshay Arun Mote from Folsom, CA, age ~38