Alak Kumar Deb

US Patent:

6393489, May 21, 2002

Filed:

Jun 13, 2000

Appl. No.:

09/594745

Inventors:

Namakkal S. Sambamurthy - San Jose CA
Devendra K. Tripathi - San Jose CA
Alak K. Deb - San Jose CA
Linh Tien Truong - San Jose CA
Praveen D. Kumar - Fremont CA

Assignee:

Vitesse Semiconductor Corporation - Camarillo CA

International Classification:

G06F 1516

US Classification:

709250, 370463

Abstract:

Disclosed is a media access controller for transferring data along a computer network. The media access controller includes a transmit media access controller that is configured to process out-going packet data received from an upper layer for transmission to a lower layer. A receive media access controller that is configured to process in-coming packet data received from the lower layer for transmission to the upper layer. A transmit multi-packet queue FIFO for receiving the out-going packet data from the upper layer before being passed to the transmit media access controller. A receive multi-packet queue FIFO for receiving the in-coming packet data that is received by the receive media access controller. The media access controller further including a media access controller manager interfacing with the transmit and receive media access controllers. The media access controller manager being responsible for managing the flow of packet data through the transmit and receive multi-packet queue FIFOs.

US Patent:

7546234, Jun 9, 2009

Filed:

Jan 7, 2004

Appl. No.:

10/753727

Inventors:

Alak Deb - San Jose CA, US
Debashis Chatterjee - San Jose CA, US

Assignee:

Xambala, inc. - San Jose CA

International Classification:

G06F 17/27
G06F 17/28
G06F 7/00
G06F 15/16

US Classification:

704 9, 704 4, 707 3, 707 10, 707102, 709201, 709230

Abstract:

A processor configured to identify message contents is provided. The processor includes a message characterization block configured to characterize a message through analysis of header information associated with the message. A semantic processing block configured to translate the message into tokens associated with segments of the message is included. The semantic processing block identifies rules associated with each of the tokens and the semantic processing block is configured to apply the identified rules to the message. A queuing block configured to queue the message to be transmitted from the processor is included. A method for providing content based security, a computer readable media, an adapter card and a network device configured to provide content based security and an intrusion protection system are provided.

US Patent:

7548848, Jun 16, 2009

Filed:

Jan 7, 2004

Appl. No.:

10/753846

Inventors:

Alak Deb - San Jose CA, US
Debashis Chatterjee - San Jose CA, US

Assignee:

Xambala, Inc. - San Jose CA

International Classification:

G06F 7/00
G06F 15/16
G06F 17/27
G06F 17/28

US Classification:

704 9, 704 4, 707 3, 707 10, 707102, 709201, 709230

Abstract:

A method for evaluating contents of a message is provided. The method initiates with characterizing a message segment. Then, the message is scanned to define tokens associated with the message segment. Next, the tokens are parsed to define substructures. Then, the rules associated with the tokens are determined, wherein the rules define actions. At the same time determining the session or meta session associated with the communication. Then, the actions associated with the message are executed. Next, the message is queued to be sent out. A method for providing content based security, a computer readable media, an adapter card and a network device configured to provide content based security and an intrusion protection system are provided.

US Patent:

7710988, May 4, 2010

Filed:

Mar 10, 2006

Appl. No.:

11/373228

Inventors:

Devendra Tripathi - San Jose CA, US
Keith Kong - San Jose CA, US
Alak Deb - San Jose CA, US
Debashis Chatterjee - San Jose CA, US

Assignee:

Xambala Corporation - San Jose CA

International Classification:

H04L 12/28

US Classification:

370411, 37039552

Abstract:

A structural matching engine for non-deterministic filtering operations is provided. The structural matching engine includes an active node processor (ANP) configured to process a state of an active list to determine possible future states of a non-deterministic finite automaton (NFA). The ANP processes the state according to rules. The structural matching engine includes an active list processor (ALP) configured to initiate a lookup for a token value corresponding to the state of the active list. The ALP provides a next sate of the active list to the ANP for processing according to the rules upon completion of the processing of the state by the ANP, wherein the possible future states of the NFA are linked by the ALP to form a target list, the target list stacked on top of the active list in a data structure. A processor and a method for filtering data associated with non-deterministic states are also included.

US Patent:

20080068998, Mar 20, 2008

Filed:

Sep 7, 2007

Appl. No.:

11/852202

Inventors:

MOHIT JAGGI - Sunnyvale CA, US
Alak Deb - San Jose CA, US

Assignee:

XAMBALA CORPORATION - San Jose CA

International Classification:

H04L 12/56

US Classification:

370232000

Abstract:

A switch including circuitry and methods for decreasing latency associated with initiating Internet communications are disclosed. The switch includes a host processor and a transport subsystem that receives incoming data and sends outgoing data. The switch also has a semantic processor. The semantic processor anticipates real-time communication by analyzing the incoming data for specific types of data from a first user in order to instruct the host processor to pre-fetch data needed to initiate real-time communications with a second user. The pre-fetching of the data needed to initiate real-time communications decreases the latency associated with establishing communications between the first user and the second user.

US Patent:

52935876, Mar 8, 1994

Filed:

Jun 1, 1990

Appl. No.:

7/532264

Inventors:

Alak K. Deb - San Jose CA
Morris E. Jones - Saratoga CA

Assignee:

Chips and Technologies, Inc. - San Jose CA

International Classification:

G06F 1562

US Classification:

395162

Abstract:

Display control logic for a terminal controller with support for such features as windows and interlace. A display list processor (DLP) (20) communicates with a program memory (12) containing DLP instructions, a display memory (12) containing character codes and attributes for the display, and a font memory (13). As the DLP program executes, it causes accesses to the display memory and brings in character codes and attributes for ultimate display on the screen. These character codes and attributes, as well as information representative of the scan line are input to a video data queue (95). The queue entries are clocked out of the queue by a character clock (170) and are used to generate addresses to font memory. Bitmaps from font memory are read into a dot shifter (190). The DLP instruction set includes a DISPLAY STRING instruction which allows a portion of a scan line to be built up by specifying the length of the scan line segment and the starting address in memory.

US Patent:

60761156, Jun 13, 2000

Filed:

Apr 24, 1997

Appl. No.:

8/845272

Inventors:

Namakkal S. Sambamurthy - San Jose CA
Devendra K. Tripathi - San Jose CA
Alak K. Deb - San Jose CA
Linh Tien Truong - San Jose CA
Praveen D. Kumar - Fremont CA

Assignee:

XAQTI Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

709250

Abstract:

Disclosed is a media access controller configured to communicate with an upper layer and a lower physical layer. The media access controller includes a receive controller for receiving and processing receive data requests from the lower layer and transferring received data to the upper layer. The method includes receiving data from the lower layer and processing the received data through the receive controller. The processor being performed in accordance with a setting of a plurality of control registers associated with the transmit controller. The method further including receiving a control signal for modifying at least one of the plurality of control registers while the data is being processed through the receive controller. Altering the processing of data being processed within the receive controller based on the modification of the at least one of the plurality of control registers associated with the receive controller, and transferring the processed data to the upper layer.

US Patent:

61729906, Jan 9, 2001

Filed:

Nov 12, 1997

Appl. No.:

8/968551

Inventors:

Alak K. Deb - San Jose CA
Namakkal S. Sambamurthy - San Jose CA
William H. Bares - Germantown TN

Assignee:

XaQti Corporation - Santa Clara CA

International Classification:

H04J 316
H04J 324

US Classification:

370474

Abstract:

Disclosed are methods and apparatus for processing packet data received from a physical layer. The processing is performed in-line while streaming packets to an upper layer. The method includes loading an instruction set for custom programming the processing of packet data received from the physical layer. Determining a type of packet data received from the physical layer. Identifying a first word location in the packet data based on the contents of the instruction set. Examining the packet data received from the physical layer at the first identified word location. The method further includes storing an element indicative of information contained in the first identified word location into a data structure, and appending the data structure to the packet data before the packet is streamed to the upper layer. The methods and apparatus also have direct applicability to reducing a CPU's work load during transmissions of data over a network.