Alan C Davis

US Patent:

20130164519, Jun 27, 2013

Filed:

Dec 22, 2011

Appl. No.:

13/334790

Inventors:

Alan DAVIS - Northport AL, US

Assignee:

RADICISPANDEX CORPORATION - Gastonia NC

International Classification:

B32B 5/02
C08K 5/20
B29C 47/88
C08G 18/32

US Classification:

428221, 525453, 525459, 524500, 524233, 26421112

Abstract:

A flame retardant polyurethane elastomer composition containing an oligomeric phosphate obtained by reaction of a trialkyl phosphate with phosphorous pentoxide and an epoxides is provided. In a preferred embodiment, the polyurethane elastomer is a spandex. A method to prepare a fiber or yarn of the flame retardant elastomer and a fabric containing the fiber or yarn is also provided.

US Patent:

20220350542, Nov 3, 2022

Filed:

Jul 18, 2022

Appl. No.:

17/867134

Inventors:

- Dallas TX, US
Duc Quang BUI - Grand Prairie TX, US
Joseph ZBICIAK - San Jose CA, US
Sahithi KRISHNA - Plano TX, US
Soujanya NARNUR - Austin TX, US
Alan DAVIS - Sugar Land TX, US

International Classification:

G06F 3/06
G06F 9/30

Abstract:

A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

US Patent:

20210334103, Oct 28, 2021

Filed:

Jul 4, 2021

Appl. No.:

17/367384

Inventors:

- Dallas TX, US
Timothy D. Anderson - University Park TX, US
Todd T. Hahn - Sugar Land TX, US
Alan L. Davis - Sugar Land TX, US

International Classification:

G06F 9/30

Abstract:

A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

US Patent:

20200379757, Dec 3, 2020

Filed:

Sep 13, 2019

Appl. No.:

16/570931

Inventors:

- Dallas TX, US
Duc BUI - Grand Prairie TX, US
Rama VENKATASUBRAMANIAN - Plano TX, US
Dheera Balasubramanian SAMUDRALA - Richardson TX, US
Alan DAVIS - Sugar Land TX, US

International Classification:

G06F 9/30
G06F 9/38

Abstract:

A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.

US Patent:

20200371711, Nov 26, 2020

Filed:

May 24, 2019

Appl. No.:

16/422250

Inventors:

- Dallas TX, US
Duc Quang BUI - Grand Prairie TX, US
Joseph ZBICIAK - San Jose CA, US
Sahithi KRISHNA - Plano TX, US
Soujanya NARNUR - Austin TX, US
Alan DAVIS - Sugar Land TX, US

International Classification:

G06F 3/06
G06F 9/30

Abstract:

A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

US Patent:

20200371762, Nov 26, 2020

Filed:

Aug 3, 2020

Appl. No.:

16/983429

Inventors:

- Dallas TX, US
Timothy D. ANDERSON - University Park TX, US
Todd T. HAHN - Sugar Land TX, US
Alan L. DAVIS - Sugar Land TX, US

International Classification:

G06F 8/41
G06F 5/06
G06F 9/30

Abstract:

A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

US Patent:

20200371800, Nov 26, 2020

Filed:

May 24, 2019

Appl. No.:

16/422823

Inventors:

- Dallas TX, US
Timothy D. ANDERSON - University Park TX, US
Todd T. HAHN - Sugar Land TX, US
Alan L. DAVIS - Sugar Land TX, US

International Classification:

G06F 9/30

Abstract:

A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.