Alan J Lawrence

US Patent:

41929730, Mar 11, 1980

Filed:

Jan 13, 1978

Appl. No.:

5/869152

Inventors:

Roger M. Williams - Maidenhead, GB2
Alan J. Lawrence - Stamford CT

Assignee:

Plessey Handel und Investments AG - 6300 Zug

International Classification:

H04Q 122
H04Q 1104

US Classification:

370 53

Abstract:

This invention is concerned with a processor-overload relief facility in a time division multiplex (t. d. m. ) processor-controlled exchanges. Under overload conditions rejection of new calls may be required until this condition is relieved and this proposal is to meet the relief function by peripheral hardware while retaining the ability to process emergency (999) calls during overload. An incoming signalling unit which is responsive to incoming seize, dialling and other signals, is provided with multi-bit stores on a one per channel basis; each such store interfacing with processor on a read/write basis. Normally the signalling unit responds to any incoming channel-seized condition and sets the `seize` bit (S) in the appropriate channel store which reports seizure to the processor. Dialled pulses are detected and accumulated in the store, and each complete digit is transferred to the processor for call control purposes. During overload conditions a common control circuit inhibits (except in the case of channel stores already receiving an S signal) certain normal transfer paths between the signalling unit and channel stores but a transfer path is left open if a 999 call is received on a level 9 circuit of the exchange, so that a new seize signal can be diverted to another storage location whereupon a "999 signal with channel identity" is transmitted to the processor.

US Patent:

42018919, May 6, 1980

Filed:

Mar 17, 1978

Appl. No.:

5/888607

Inventors:

Alan J. Lawrence - Stamford CT
John M. Cotton - East Norwalk CT
Jeffrey N. Denenberg - Stamford CT

Assignee:

International Telephone and Telegraph Corporation - New York NY

International Classification:

H04Q 1104

US Classification:

370 58

Abstract:

A distributed control digital switching network is configured as a group switch having a plurality of stages of multiport single sided switching elements for selectively interconnecting a plurality of input terminals via the transmission paths established through the network by path selection control signals which are multiplexed on common transmission links to and through the network together with digitally encoded data from the terminals on common transmission paths such that data is received phase asynchronously at each stage of the network and is either coupled to a higher order stage of the network or folded back through the network by reflection to interconnect terminals switched by the network. The single-sided switching elements are selectively operable as single-sided or multi-sided in accordance with their position in the network.

US Patent:

42018897, May 6, 1980

Filed:

Mar 17, 1978

Appl. No.:

5/888251

Inventors:

Alan J. Lawrence - Stamford CT
John M. Cotton - East Norwalk CT
Kenneth J. Hamer-Hodges - Newtown CT
Jeffrey N. Denenberg - Stamford CT

Assignee:

International Telephone and Telegraph - New York NY

International Classification:

H04Q 1104

US Classification:

320 68

Abstract:

A distributed control digital switching system is described in which a plurality of subscriber lines and trunks are provided with a switched access to various processing functions shared over a plurality of time shared multiplexed lines. Each processor of a first group of processors is dedicated to a group of terminals such as subscriber lines or trunks, and communicate with processors in a second group to provide pooled processing functions to one or more of said groups of terminals through a digital switching matrix. Processors in the first group perform a first set of processing functions, such as path set up and processors of the second group perform a second set of processing functions, such as call control. A multistage switching network provides a modularly expandable digital group switch, the operation of which is controlled externally from the terminals to which it is connected, and provides rate synchronous, phase (bit) asynchronous interconnection among the terminals which are interfaced and switched. Each processor of the first group is time shared over a security block of lines or trunks providing hardware interface therebetween while each processor of the second group provides pooled functions for a plurality of security blocks of lines and trunks.

US Patent:

42018900, May 6, 1980

Filed:

Mar 17, 1978

Appl. No.:

5/888582

Inventors:

Alan J. Lawrence - Stamford CT
Jeffrey N. Denenberg - Stamford CT
Murray Rubinstein - Trumbull CT
Daniel C. Upp - Easton CT

Assignee:

International Telephone and Telegraph - New York NY

International Classification:

H04J 306
H04Q 1104

US Classification:

370 68

Abstract:

A multiport single sided switching element is described for providing space and time switching between the input ports thereof and the output ports thereof in response to digital command signals for frames of digitally encoded data in a plurality of channels which is phase (bit) asynchronously coupled to any port of the switching element, the command signals being in for example the same channels as is the data. Every port of the single sided switching element is adaptable as either an inlet or an outlet and thus may be configured in a switching network as a one-sided, as a two-sided, or multisided switching element and includes a time division multiplexed bus for providing a space path between the ports of the switching element and further includes transmit and receive logic at each port responsive to command signals for coupling data from the input of any port to the TDM bus and additional logic at each port selectively responsive to command signals for bit synchronously extracting the data from the TDM bus in any channel thereby providing time slot interchange prior to coupling of data from the switching element to other switching elements. In a preferred embodiment, a sixteen port switching element is described.