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Alan L Westwick

age ~60

from Austin, TX

Also known as:
  • Alan Westwick
  • Alan Lee Westwick
3418 Rosefinch Trl, Austin, TX 78746(512)3287060

Alan Westwick Phones & Addresses

  • 3418 Rosefinch Trl, Austin, TX 78746 • (512)3287060
  • Lexington, KY
  • Georgetown, TX
  • Dripping Springs, TX
  • Hays, TX
  • 3418 Rosefinch Trl, Austin, TX 78746 • (512)6578523

Industries

Semiconductors

Resumes

Alan Westwick Photo 1

Alan Westwick

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Location:
Austin, Texas Area
Industry:
Semiconductors

Us Patents

  • Circuit And Method Of Establishing Dc Bias Levels In An Rf Power Amplifier

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  • US Patent:
    7064605, Jun 20, 2006
  • Filed:
    Dec 22, 2003
  • Appl. No.:
    10/743221
  • Inventors:
    Alan L. Westwick - Austin TX,
    Susanne A. Paul - Austin TX,
  • Assignee:
    Silicon Laboratories Inc. - Austin TX
  • International Classification:
    H03F 1/34
    H03G 3/20
  • US Classification:
    330 85, 330136
  • Abstract:
    A method and apparatus is used to provide DC stabilization and noise reduction in a multistage power amplifier. The invention uses various feedback techniques to stabilize DC levels, which helps to reduce noise. The invention also uses other techniques to reduce noise, and to reduce the noise transfer function in a power amplifier.
  • Cmos Amplifier Circuit Which Minimizes Power Supply Noise Coupled Via A Substrate

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  • US Patent:
    47852585, Nov 15, 1988
  • Filed:
    Sep 17, 1987
  • Appl. No.:
    7/097765
  • Inventors:
    Alan L. Westwick - Austin TX
  • Assignee:
    Motorola, Inc. - Schaumburg IL
  • International Classification:
    H03F 345
  • US Classification:
    330253
  • Abstract:
    A CMOS circuit having a differential input stage which provides a single output is provided. An output stage has a capacitor which is used as a Miller integrator coupled thereto for frequency stabilization. A cascode portion is coupled to the Miller integrator to maintain one of the capacitor's electrodes at a predetermined voltage potential. A compensation portion is coupled to the cascode portion to compensate for power supply induced errors created when either an N-channel transistor in an N-well process or a P-channel transistor in a P-well process is used in the cascode portion.
  • Analog Interface For A Microprocessor-Based Device

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  • US Patent:
    20120173787, Jul 5, 2012
  • Filed:
    Dec 30, 2010
  • Appl. No.:
    12/981741
  • Inventors:
    Alan L. Westwick - Austin TX,
    Thomas S. David - Austin TX,
  • International Classification:
    G06F 13/20
  • US Classification:
    710313
  • Abstract:
    An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit.
  • Voltage Regulator With Adjustable Feedback

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  • US Patent:
    20130221937, Aug 29, 2013
  • Filed:
    Feb 24, 2012
  • Appl. No.:
    13/404981
  • Inventors:
    Shouli Yan - Austin TX,
    Alan Westwick - Austin TX,
  • International Classification:
    G05F 1/10
  • US Classification:
    323271
  • Abstract:
    A voltage regulator circuit with variable feedback is disclosed. In one embodiment, a voltage regulator includes an amplifier having a first input configured to receive a reference voltage and a second input configured to receive a feedback signal. The voltage regulator further includes first and second transistors each having respective gate terminals coupled to an output of the amplifier. A resistor network coupled to the second input of the amplifier and further coupled to the first and second transistors. The resistor network is configured to produce the feedback signal based on currents through the first and second transistors, respectively.
  • Linear Regulator

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  • US Patent:
    20130221940, Aug 29, 2013
  • Filed:
    Feb 24, 2012
  • Appl. No.:
    13/404558
  • Inventors:
    Shouli Yan - Austin TX,
    Dazhi Wei - Austin TX,
    Alan L. Westwick - Austin TX,
  • International Classification:
    G05F 1/10
  • US Classification:
    323273
  • Abstract:
    A technique includes using a pass device of a linear regulator to provide an output signal for the linear regulator in response to a signal that is received at a control terminal of the pass device. The control terminal is coupled to a node, and the node is associated with a bias current. The technique includes using a feedback path to communicate a feedback current with the node to regulate the output signal. The use of the feedback path includes regulating a magnitude of the feedback current to be within a range of magnitudes, which include a magnitude that exceeds a magnitude of the bias current.
  • Integrated Circuit, System, And Method Including A Shared Synchronization Bus

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  • US Patent:
    20130227181, Aug 29, 2013
  • Filed:
    Feb 28, 2012
  • Appl. No.:
    13/407721
  • Inventors:
    Bradley Martin - Austin TX,
    Thomas Saroshan David - Austin TX,
    Alan Lee Westwick - Austin TX,
  • International Classification:
    G06F 13/14
  • US Classification:
    710 58
  • Abstract:
    An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.
  • Digital-To-Analog Converter Resolution Enhancement Using Circular Buffer

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  • US Patent:
    20130249724, Sep 26, 2013
  • Filed:
    Mar 22, 2012
  • Appl. No.:
    13/427740
  • Inventors:
    Alan Westwick - Austin TX,
    Sebastian Ahmed - Austin TX,
  • International Classification:
    H03M 1/20
  • US Classification:
    341131
  • Abstract:
    A system and method for generating an analog signal is disclosed. In one embodiment, system includes a first-in, first-out (FIFO) buffer configured to receive and store a plurality of digital values written to the FIFO buffer. The system further includes a digital-to-analog converter (DAC) coupled to read the digital values from the FIFO buffer and configured to convert the digital values to an analog signal. The FIFO buffer is configured to operate in a first mode in which writes to the FIFO buffer are inhibited and current digital values stored in the FIFO buffer are provided to the DAC in a repeating sequence.
  • Apparatus For Improved Signal Communication In Electronic Circuitry And Associated Methods

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  • US Patent:
    20140002162, Jan 2, 2014
  • Filed:
    Mar 14, 2013
  • Appl. No.:
    13/831432
  • Inventors:
    Alan Westwick - Austin TX,
  • Assignee:
    SILICON LABORATORIES INC. - Austin TX
  • International Classification:
    H03K 3/01
  • US Classification:
    327205
  • Abstract:
    An apparatus includes a microcontroller unit (MCU). The MCU includes a buffer and an analog comparator that are coupled to an input of the MCU. The MCU is adapted to selectively determine a logic value of a digital signal applied to the input of the MCU from an output signal of the buffer or from an output signal of the analog comparator.

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