Albert M Thaik

US Patent:

53176014, May 31, 1994

Filed:

Aug 21, 1992

Appl. No.:

7/933467

Inventors:

Thomas J. Riordan - Los Altos CA
Albert M. Thaik - San Jose CA
Hai N. Nguyen - Milpitas CA

Assignee:

Silicon Graphics - Mountain View CA

International Classification:

H04L 700
H03K 700
H03K 1700
H03K 1726

US Classification:

375107

Abstract:

Techniques for providing a number of precisely synchronized clock signals at a number of different frequencies at each of a plurality of locations on a chip. A number of synchronized clock signals are generated at an initial location on the chip, and distributed to the various locations with relative delay times that are equal to within a precision, which may be less than the ultimate precision required. A single synchronization signal is also generated at the initial location, and is distributed to the remote locations with delay times that are equal to each other to a precision that corresponds to the precision required of all the clock signals. Separate synchronization circuitry at each remote location receives the clock signals and the synchronization signal, and resynchronizes the clock signals to the precision with which the synchronization signal was distributed. The set of lines is configured as a tree structure. The clock generation system has a cycle-down mode wherein all the clock frequencies are divided by a desired divisor.

US Patent:

59789263, Nov 2, 1999

Filed:

Mar 9, 1998

Appl. No.:

9/036684

Inventors:

Paul S. Ries - San Jose CA
John R. Kinsel - San Jose CA
Thomas J. Riordan - Los Altos CA
Albert M. Thaik - San Jose CA

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

G06F 108

US Classification:

713501

Abstract:

Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.

US Patent:

52851168, Feb 8, 1994

Filed:

Aug 28, 1990

Appl. No.:

7/573926

Inventors:

Albert Thaik - Cupertino CA

Assignee:

MIPS Computer Systems, Inc. - Sunnyvale CA

International Classification:

H03K 19017

US Classification:

307443

Abstract:

A low-noise high-speed output buffer receives digital control signals for varying the switching delay and di/dt of the buffer. For a plurality of output buffers, one buffer is used to determine the digital control signal values for the rest. The switching delay is controlled by referencing the one output buffer's delay to a clock cycle (e. g. , 0. 75 T or T, where T equals the clock cycle period). The digital control signal values which define the delay with reference to the clock cycle also determine the di/dt for the output buffers. As process or operating conditions vary, the control signal values change to maintain the delay in the prescribed relation to the clock cycle. Accordingly, the absolute di/dt values change. Thus, the output signal is available by the time needed (e. g. , 0. 75 T), while the di/dt is varied to an optimum setting based on the absolute delay time.

US Patent:

57348774, Mar 31, 1998

Filed:

Sep 19, 1996

Appl. No.:

8/715246

Inventors:

Paul S. Ries - San Jose CA
John R. Kinsel - San Jose CA
Thomas J. Riordan - Los Altos CA
Albert M. Thaik - San Jose CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 104

US Classification:

395555

Abstract:

Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.