Albert K Wu

US Patent:

6876031, Apr 5, 2005

Filed:

Feb 23, 1999

Appl. No.:

09/256265

Inventors:

Dah-Bin Kao - Palo Alto CA, US
Loc B. Hoang - San Jose CA, US
Albert T. Wu - Palo Alto CA, US

Assignee:

Winbond Electronics Corporation - Hsin chu

International Classification:

H01L029/788
G11C016/04

US Classification:

257315, 257317, 36518501, 36518526, 36518529

Abstract:

A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.

US Patent:

6940107, Sep 6, 2005

Filed:

Dec 12, 2003

Appl. No.:

10/734779

Inventors:

Chuan-Cheng Cheng - Fremont CA, US
Shuhua Yu - Cupertino CA, US
Roawen Chen - San Jose CA, US
Albert Wu - Palo Alto CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H01L027/10

US Classification:

257209, 257529, 257530

Abstract:

A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

US Patent:

7288845, Oct 30, 2007

Filed:

May 8, 2003

Appl. No.:

10/434524

Inventors:

Sehat Sutardja - Los Altos Hills CA, US
Albert Wu - Palo Alto CA, US
Jin-Yuan Lee - Hsin-chu, TW
Mou-Shiung Lin - Hsin-chu, TW

Assignee:

Marvell Semiconductor, Inc. - Sunnyvale CA
MEGIC Corporation - Hsinchu

International Classification:

H01L 23/485

US Classification:

257781, 257786, 257784, 257E2302

Abstract:

A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.

US Patent:

7292005, Nov 6, 2007

Filed:

Feb 3, 2006

Appl. No.:

11/347791

Inventors:

Steven M Pietkiewicz - Fremont CA, US
Albert M Wu - Sunnyvale CA, US

Assignee:

Linear Technology Corp. - Milpitas CA

International Classification:

H01M 10/44
H01M 10/46

US Classification:

320166

Abstract:

The present invention provides a capacitor charging circuit that efficiently charges capacitive loads. In particular, circuits and techniques are preferably provided for using current from both the primary and secondary windings of a transformer to control ON-time and OFF-time of a switch. This arrangement preferably yields an adaptable ON-time and adaptable OFF-time switch that is capable of rapidly charging capacitor loads ranging from as low as zero volts to several hundred volts. The output voltage is preferably measured indirectly to prevent unnecessary power consumption. In addition, control circuitry can be provided to conserve power by ceasing the delivery of power to the capacitor load once the desired output voltage is reached. Control circuitry preferably operates an interrogation timer that periodically activates the power delivery cycle to maintain the capacitor output load in a constant state of readiness.

US Patent:

7344924, Mar 18, 2008

Filed:

May 24, 2005

Appl. No.:

11/136925

Inventors:

Chuan-Cheng Cheng - Fremont CA, US
Shuhua Yu - Cupertino CA, US
Roawen Chen - San Jose CA, US
Albert Wu - Palo Alto CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H01L 21/82

US Classification:

438129, 438132, 438215, 257209

Abstract:

A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

US Patent:

7359261, Apr 15, 2008

Filed:

Feb 7, 2006

Appl. No.:

11/349460

Inventors:

Albert Wu - Palo Alto CA, US
Sehat Sutardja - Los Altos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11C 7/00

US Classification:

365200, 365201, 36523006

Abstract:

An IC includes a memory module that stores at least one of data and code. A memory repair database stores data relating to defective memory addresses. A memory control module communicates with the memory module and the memory repair database, detects defective memory locations in the memory module, locates redundant memory elements in the memory module, stores information that associates memory addresses of the defective memory locations with the redundant memory elements in the memory repair database, and outputs the information. The memory control module includes a plurality of electrical fuses. Storing the information includes electrically altering at least one of the plurality of electrical fuses. A redundant memory decoder module receives the information and physically remaps the memory addresses to the redundant memory locations.

US Patent:

7535110, May 19, 2009

Filed:

May 9, 2007

Appl. No.:

11/801317

Inventors:

Albert Wu - Palo Alto CA, US
Huahung Kao - San Jose CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

H01L 23/48

US Classification:

257778, 257777, 438108

Abstract:

Integrated circuit packages having corresponding methods comprise: a substrate comprising first electric contacts; a first wirebond integrated circuit die mechanically coupled to the substrate and comprising second electric contacts electrically coupled to the first electric contacts of the substrate by first electrically conductive wires; a flip-chip integrated circuit die comprising third electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die by electrically conductive bumps; and a second wirebond integrated circuit die mechanically coupled to the flip-chip integrated circuit die and comprising fourth electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die, or the first electric contacts of the substrate, or both, by second electrically conductive wires.

US Patent:

7589363, Sep 15, 2009

Filed:

May 22, 2007

Appl. No.:

11/805290

Inventors:

Chuan-Cheng Cheng - Fremont CA, US
Shuhua Yu - Cupertino CA, US
Roawen Chen - San Jose CA, US
Albert Wu - Palo Alto CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H01L 27/10
H01L 29/00

US Classification:

257209, 257529, 257530, 438129

Abstract:

A structure configured to disconnect circuit elements. The structure generally includes a dielectric layer over a light-absorbing structure, and a lens over the dielectric layer and the light-absorbing structure, configured to at least partially focus light onto the light-absorbing structure. The light-absorbing structure absorbs a first wavelength of light with a minimum threshold efficiency, the lens is substantially opaque to the first wavelength of light, and the dielectric layer is substantially transparent to the first wavelength of light. The structure advantageously provides improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).