A interface, which connects memory and an integrated circuit, having a write path and read path that allow synchronous data propagation is provided. Further, a method for synchronizing data propagation through a read path and a write path of an interface is provided. The interface uses clock signals and paths based on a clock signal to synchronize the flow of data through various paths within the interface.
Michael G. Lavelle - Saratoga CA Alex N. Koltzoff - Sausalito CA David C. Kehlet - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G06F 1520
US Classification:
371 224
Abstract:
A method and apparatus for performing signature analysis of video data being output by a RAMDAC so that starting and stopping the sampling of data is made precise so that the data sampled is a known set. The invention uses a timing generator and signature analysis hardware integrated with a RAMDAC to start and stop the sampling and signature calculation of video data on frame boundaries. A signature capture request bit is used to request that the next frame be sampled and a signature calculated. The hardware waits until the beginning of the next frame starts, and then samples data until the frame ends. The calculated signature is made available in a signature analysis result register for reading. The resulting signature is held in the signature analysis result register until cleared or another signature capture request is made.
Michael G. Lavelle - Saratoga CA Alex N. Koltzoff - Sausalito CA David C. Kehlet - Sunnyvale CA
Assignee:
Sun Microsystems Inc. - Mountain View CA
International Classification:
G09G 504
US Classification:
345154
Abstract:
A method and for multiplexing pixel data from a frame buffer to a RAMDAC to reduce the number of pins required. For many graphics operations optimal performance is achieved by storing an entire 32-bit pixel in a single RAM chip. When displaying video data from a frame buffer, pixels must be read out serially from the frame buffer at real-time speeds. A frame buffer memory with 16 pins for serial video output is used. An entire 32-bit pixel is stored in a single RAM chip. For a 32-bit pixel containing four byte (8-bit) quantities designated X, B, G and R, on the first clock cycle, the X and B bytes are made available on the 16 pins of the frame buffer. On the next clock cycle, the G and R bytes are made available. Thus, over two cycles the entire 32-bit pixel is output from the frame buffer to a RAMDAC which samples the X and B bytes on 16 input pins. The RAMDAC stores these X and B bytes in an internal register.
Fast Frame Buffer System Architecture For Video Display System
Michael Lavelle - Saratogo CA Alex Koltzoff - Corte Madera CA David Kehlet - Los Altos CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G09G 536
US Classification:
345509
Abstract:
A fast frame buffer system and architecture supports preferably 24-bit capability and includes an integer rendering pipeline, especially useful for three-dimensional applications. The system includes a frame buffer random access memory system ("FBRAM") that includes video source data and is configurable as a single-buffer or double-buffer, a fast frame buffer controller integrated circuit ("FFB ASIC") that includes system command and video refresh control functions, and a random access memory digital-to-analog converter unit ("RAMDAC") that includes the buffer system timing generator. A FBRAM controller unit provides both parallel accelerated rendering pipeline and direct access paths to the FBRAM unit. The timing generator outputs serial clock and serial clock enable signals, the latter signal preceding horizontal blanking signals by preferably N=1 serial clock pulses to compensate for pixel signal path timing delays.
Video Frame Synchronization Of Independent Timing Generators For Frame Buffers In A Master-Slave Configuration
Michael F. Deering - Los Altos CA Michael G. Lavelle - Saratoga CA Alex N. Koltzoff - Sausalito CA David C. Kehlet - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G09G 500
US Classification:
345213
Abstract:
A method and apparatus for synchronizing the vertical blanking of multiple frame buffers which may exist on the same computer or separate computers for certain applications including stereo display, virtual reality and video recording, which require such synchronization. To obtain the required synchronization one frame buffer is designation as the master. It provides a signal called FIELD that changes state (0 to 1 or 1 to 0) at the start of every vertical sync event on the master frame buffer. All other frame buffers are set to be slaves. Their timing generators sample the master's FIELD signal. When they detect the master's FIELD signal changing state, they set their own internal timing to match to thereby achieve frame synchronization.
Frame Buffer System With Non-Overlapping Pixel Buffer Access Variable Interleaving, Nibble Replication
Darko DeGoricija - San Jose CA Michael Andrew Ekberg - Atherton CA Alex Koltzoff - Sausalito CA Charles Srethabhakti - San Jose CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G09G 536
US Classification:
345507
Abstract:
A frame buffer system is disclosed that employs non overlapping serial enable signals to access pixel data values from sets of pixel buffers contained in each interleave of a multiple interleave frame buffer according to the attribute data in the frame buffer. The frame buffer system provides circuitry for varying the interleave factor between frame buffer accesses and the generation of corresponding video data. The frame buffer system also provides circuitry for expanding double buffered pixel data values into full addressing for color look-up.