Alex B Sanville

US Patent:

7711869, May 4, 2010

Filed:

Dec 20, 2007

Appl. No.:

11/960759

Inventors:

Stephen E. Strickland - Foxboro MA, US
Alex Joseph Sanville - Chelmsford MA, US
Douglas Sullivan - Hopkinton MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 3/00
G06F 11/00

US Classification:

710 15, 710104, 710 8, 710301, 713 1, 714 21

Abstract:

A system having a processor, a printed circuit board, and an adapter board, coupled to the processor through the printed circuit board. The adapter board provides a first signal having a first state when the adapter board is in a proper operating condition and a second state when the adapter board is in an improper condition. The adapter board produces a second signal having the second state for less than a predetermined time when an adapter board requires a reset signal from the processor. The adapter board combines the first signal with the second signal a single signal fed to the processor through the printed circuit board. When the processor detects that the single signal is in the second state for a time less than the predetermined period of time, the process interprets the single signal as indicating the adapter board requires a reset.

US Patent:

7809964, Oct 5, 2010

Filed:

Sep 28, 2007

Appl. No.:

11/863882

Inventors:

Stephen Strickland - Foxboro MA, US
Alex Joseph Sanville - Chelmsford MA, US
Douglas Richard Sullivan - Hopkinton MA, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 1/00
G06F 9/00
G06F 3/00
G06F 13/12
G06F 13/00
H05K 7/10

US Classification:

713300, 713 1, 713100, 713330, 713340, 710 8, 710 15, 710 62, 710301, 711100

Abstract:

An I/O interface module of a storage system controller includes a management controller and power regulation and monitoring/control circuitry responsible for management of the I/O expansion module and pluggable I/O interface modules, which each include electrical power regulating circuitry to power circuit components. Temperature regulation components (e. g. fan and temperature sensor) provide a cooling airflow and monitor operating temperature. A controller works with the power regulation and monitor/control circuitry and temperature regulation components to perform first and second management activities concurrently. The first management activity involves managing the environmental operating conditions of the I/O expansion module itself, including (i) monitoring and regulating operating temperature and (ii) monitoring and controlling electrical power regulating circuitry of the power regulation and monitor/control circuitry. The second management activity involves managing environmental operating conditions of the I/O interface module, including (i) monitoring insertion and removal of the I/O interface module and reporting such insertion and removal to a separate controller within the storage system controller, (ii) controlling reset status of the I/O expansion module, and (iii) monitoring and controlling the electrical power regulating circuitry of the I/O interface module.

US Patent:

7809975, Oct 5, 2010

Filed:

Mar 29, 2007

Appl. No.:

11/729728

Inventors:

David French - Grafton MA, US
Douglas Sullivan - Hopkinton MA, US
William Buckley - Brighton MA, US
Alex Sanville - Boxborough MA, US
Phillip J. Manning - East Geenwich RI, US

Assignee:

EMC Corporation - Hopkinton MA

International Classification:

G06F 11/00

US Classification:

714 3

Abstract:

A computerized system includes two storage processors having respective local write caches configured to mirror each other. When a first storage processor becomes unavailable and mirroring of the local write caches is prevented, the computerized system continues to attend to write operations from an external host in a write-back manner by caching write data from the write operations in the local write cache of the second storage processor. In response to a failure of the second storage processor, the computerized system preserves the write data within the local write cache of the second storage processor. Then, upon recovery of the second storage processor from the failure, the computerized system continues to attend to further write operations from the external host in the write-back manner by caching additional write data in the local write cache of the second storage processor while the first storage processor remains unavailable.