Alexander L Iles

US Patent:

7366803, Apr 29, 2008

Filed:

Feb 23, 2005

Appl. No.:

11/063489

Inventors:

Justin L. Gaither - Austin TX, US
Alexander Linn Iles - Austin TX, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 13/00
G06F 3/00
H04L 12/28

US Classification:

710 54, 710 1, 710 4, 710 52, 710 57, 710 65, 370363, 370412, 370505

Abstract:

A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of consecutive sequence ordered sets, from the stream of data blocks to create a first modified data stream which is coupled to a memory device. Finally, a second circuit coupled to the memory device generates a second modified data stream using a second clock signal. The second modified data stream preferably comprises the data blocks of the first modified data stream and idle data blocks inserted among the data blocks of the first modified data stream. Methods of buffering data received in a first clock domain and output in a second clock domain are also disclosed.

US Patent:

58130438, Sep 22, 1998

Filed:

Jul 12, 1996

Appl. No.:

8/678898

Inventors:

Alexander L. Iles - Austin TX
Rand L. Gray - Austin TX
Weilming Sieh - Natick MA
Michael D. Walker - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1200
G06F 1300
G06F 1120

US Classification:

711163

Abstract:

A data processing system (100, 300) allows an individually mappable word of memory to patch a desired memory location. During operation, a memory system (130) monitors an address/control bus to determine when an access to a specified word in a system memory (120) occurs. When an access to the specified word occurs, address comparators (140) determine if a memory location to be patched is being accessed, and provides an active signal to the access control circuit (150), which prevents data flow with the system memory (120) and enables the data flow with a separate memory (170) by controlling a transmission gate 115. Therefore, the data access occurs from the separate memory and not the system memory.

US Patent:

55487947, Aug 20, 1996

Filed:

Dec 5, 1994

Appl. No.:

8/349286

Inventors:

Oded Yishay - Austin TX
Joseph Jelemensky - Austin TX
Alexander L. Iles - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1340
G06F 934

US Classification:

395871

Abstract:

A data processor (10) and method which provides show-cycles on a fast multiplexed bus (28) using two distinct modes of operation. A first mode of operation supports a standard show-cycle on a multiplexed bus for interface to a passive device such as a logic analyzer (100). A second mode of operation supports emulation tools (100) with real-time tracking of control functions using a multiplexed bus. During each of the modes of operation of the data processor (10), both read and write show cycles are supported and are consistently provided in a similar format.

US Patent:

55748945, Nov 12, 1996

Filed:

Nov 3, 1994

Appl. No.:

8/333658

Inventors:

Alexander L. Iles - Austin TX
Joseph Jelemensky - Austin TX
Oded Yishay - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 104

US Classification:

395555

Abstract:

An integrated circuit terminal of a data processing system (10) is used to communicate multiplexed signals with an external device. During a reset operation in which a reset signal is asserted, a desired internal clock signal is driven to the integrated circuit terminal such that an emulation system (52) may use the internal clock signal to synchronize an emulation operation. After the reset signal is negated, the emulation system synthesizes the internal clock signal for use during emulation. External visibility of a write operation to a register which controls pertinent signal parameters is provided via other integrated circuit terminals when the data processor operates in an emulation mode. The external visibility allows the development system to make similar changes to corresponding signal parameters therein. Therefore, the development system is able to accurately synchronize an emulation operation even when signal parameters are modified during operation.

US Patent:

20140168447, Jun 19, 2014

Filed:

Dec 18, 2012

Appl. No.:

13/718764

Inventors:

TRACKINGPOINT, INC. - , US
John Francis McHale - Austin TX, US
Alexander Linn Iles - Austin TX, US
John Hancock Lupher - Austin TX, US
Michael Eric Reimers - Austin TX, US

Assignee:

TRACKINGPOINT, INC. - Austin TX

International Classification:

H04N 5/232

US Classification:

348169

Abstract:

An optical device for use with a firearm includes an image sensor configured to capture visual data corresponding to video of a view area, and includes a display, and a controller coupled to the image sensor and to the display. The controller is configured to provide the video including a visual marker at a previously selected tag location on a target within the video to a display. The controller is configured to reapply the visual marker to the previously selected tag location on the target within the video, shot after shot, when the controller is in a group shooting mode.