Alexander T Kan

US Patent:

8085280, Dec 27, 2011

Filed:

Feb 14, 2011

Appl. No.:

13/027210

Inventors:

Loren Brichter - San Jose CA, US
Alexander King-Chung Kan - Mountain View CA, US
Michael James Elliott Swift - Mountain View CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G09G 5/00

US Classification:

345660, 345661, 345667, 345668

Abstract:

A method and an apparatus for determining an up scale factor and a down scale factor according to a scale factor received from a graphics application program interface (API) to scale a graphics data in a graphics processing unit (GPU) are described. The up scale factor and the down scale factor may be precisely stored in the GPU based on a fixed number of bits. An actual scale factor which can be precisely stored in the GPU corresponding to the scale factor may differ from the scale factor with a difference. Graphics commands may be sent to the GPU to scale the graphics data according to the up scale factor and the down scale factor separately. A combined scale factor corresponding to a combination of the up scale factor and the down scale factor may differ from the scale factor less then the difference between the actual scale factor and the scale factor.

US Patent:

20080303846, Dec 11, 2008

Filed:

Jun 7, 2007

Appl. No.:

11/811195

Inventors:

Loren Brichter - San Jose CA, US
Alexander King-Chung Kan - Mountain View CA, US
Michael James Elliott Swift - Mountain View CA, US

International Classification:

G09G 5/00
G06T 1/00
G09G 5/36

US Classification:

345661, 345522, 345559

Abstract:

A method and an apparatus for determining an up scale factor and a down scale factor according to a scale factor received from a graphics application program interface (API) to scale a graphics data in a graphics processing unit (GPU) are described. The up scale factor and the down scale factor may be precisely stored in the GPU based on a fixed number of bits. An actual scale factor which can be precisely stored in the GPU corresponding to the scale factor may differ from the scale factor with a difference. Graphics commands may be sent to the GPU to scale the graphics data according to the up scale factor and the down scale factor separately. A combined scale factor corresponding to a combination of the up scale factor and the down scale factor may differ from the scale factor less then the difference between the actual scale factor and the scale factor

US Patent:

20130293544, Nov 7, 2013

Filed:

May 3, 2012

Appl. No.:

13/462921

Inventors:

Richard W. Schreyer - Scotts Valley CA, US
Alexander K. Kan - San Francisco CA, US

International Classification:

G06T 15/60
G06T 15/20

US Classification:

345426, 345427

Abstract:

An image may be divided into tiles, each tile including a multitude of pixels. For each tile, a list of primitive groups that intersect the tile and an initial list of volumes that intersect the tile may be generated. For each primitive group in the list of primitive groups, a per-primitive group list of volumes may be generated. The per-primitive-group list of volumes may include volumes from the initial list of volumes whose depth range overlaps with a depth range of the primitive group. Pixels in the tile which intersect the primitive group may be shaded using the per-primitive-group list of volumes.

US Patent:

20230077843, Mar 16, 2023

Filed:

Aug 12, 2022

Appl. No.:

17/887222

Inventors:

- Cupertino CA, US
Mehmet N Agaoglu - Dublin CA, US
Gokhan Avkarogullari - San Jose CA, US
Jenny Hu - Sunnyvale CA, US
Alexander K Kan - San Carlos CA, US
Yuhui Li - Cupertino CA, US
James R Montgomerie - Sunnyvale CA, US
Andrey Pokrovskiy - Mountain View CA, US
Yingying Tang - Cupertino CA, US
Chaohao Wang - Shanghai, CN

International Classification:

G09G 5/36

Abstract:

An electronic device may include a display. Control circuitry may operate the display at different frame rates such as 60 Hz, 80 Hz, and 120 Hz. The control circuitry may determine which frame rate to use based on a speed of animation on the display and based on a type of animation on the display. To mitigate the appearance of judder as the display frame rate changes, the control circuitry may implement techniques such as hysteresis (e.g., windows of tolerance around speed thresholds to ensure that the display frame rate does not change too frequently as a result of noise), speed thresholds that are based on a user perception study, consistent latency between touch input detection and corresponding display output across different frame rates (e.g., using a fixed touch scan rate that is independent of frame duration), and animation-specific speed thresholds for triggering frame rate changes.

US Patent:

20210134045, May 6, 2021

Filed:

Jan 15, 2021

Appl. No.:

17/150472

Inventors:

- Cupertino CA, US
Richard W. Schreyer - Scotts Valley CA, US
James J. Ding - Santa Clara CA, US
Alexander K. Kan - San Francisco CA, US
Michael Imbrogno - San Jose CA, US

International Classification:

G06T 15/00
G06F 12/00

Abstract:

Techniques are disclosed relating to specifying memory consistency constraints. In some embodiments, an instruction may specify, for a memory operation, a type of memory consistency and a scope at which to enforce the type of consistency. For example, these fields may specify whether to sequence memory accesses relative to the operation at one or more of multiple different cache levels based on the type of memory consistency and the scope.

US Patent:

20200242726, Jul 30, 2020

Filed:

Apr 16, 2020

Appl. No.:

16/850101

Inventors:

- Cupertino CA, US
Sean P. James - Sunnyvale CA, US
Gokhan Avkarogullari - San Jose CA, US
Alexander K. Kan - Huntington Woods MI, US
Michael Imbrogno - San Jose CA, US

International Classification:

G06T 1/60
G06F 9/448
G09G 5/36
G06T 15/04
G06F 3/14
G06T 15/00
G06T 1/20

Abstract:

The disclosure pertains to techniques for operation of graphics systems and task execution on a graphics processor. One such technique comprises a computer-implemented method for task execution on a graphics processor, the method comprising creating a data structure for grouping data resources, populating the data structure with two or more data resources for encoding into a graphics processing language by an encoding object, passing the data structure to a first programming interface command, the first programming interface command configured to access the data structure's data resources, triggering execution of a first function on a graphics processer in response to passing the data structure to the first programming interface command, passing the data structure to a second programming interface command, the second programming interface command configured to access the data structure's data resources, and triggering execution of a second function on the graphics processer in response to passing the data structure to the second programming interface command.

US Patent:

20200167986, May 28, 2020

Filed:

Dec 9, 2019

Appl. No.:

16/707455

Inventors:

- Cupertino CA, US
Richard W. Schreyer - Scotts Valley CA, US
James J. Ding - Santa Clara CA, US
Alexander K. Kan - San Francisco CA, US
Michael Imbrogno - San Jose CA, US

International Classification:

G06T 15/00
G06F 12/00

Abstract:

Techniques are disclosed relating to synchronizing access to pixel resources. Examples of pixel resources include color attachments, a stencil buffer, and a depth buffer. In some embodiments, hardware registers are used to track status of assigned pixel resources and pixel wait and pixel release instruction are used to synchronize access to the pixel resources. In some embodiments, other accesses to the pixel resources may occur out of program order. Relative to tracking and ordering pass groups, this weak ordering and explicit synchronization may improve performance and reduce power consumption. Disclosed techniques may also facilitate coordination between fragment rendering threads and auxiliary mid-render compute tasks.

US Patent:

20190251656, Aug 15, 2019

Filed:

Apr 22, 2019

Appl. No.:

16/390577

Inventors:

- Cupertino CA, US
Kenneth C. Dyke - Los Altos CA, US
Alexander K. Kan - San Francisco CA, US

International Classification:

G06T 1/20
G06F 9/54
G06F 9/30

Abstract:

Systems, computer readable media, and methods for a unified programming interface and language are disclosed. In one embodiment, the unified programming interface and language assists program developers write multi-threaded programs that can perform both graphics and data-parallel compute processing on GPUs. The same GPU programming language model can be used to describe both graphics shaders and compute kernels, and the same data structures and resources may be used for both graphics and compute operations. Developers can use multithreading efficiently to create and submit command buffers in parallel.