Allan L Goodman

US Patent:

48069213, Feb 21, 1989

Filed:

Oct 4, 1985

Appl. No.:

6/784856

Inventors:

Allan L. Goodman - Hillsboro OR
Morris H. Green - Milwauki OR
Matthew J. Jolley - Hillsboro OR
Robin L. Teitzel - Portland OR
John L. Wipfli - Hillsboro OR

Assignee:

ATEQ Corporation - Beaverton OR

International Classification:

G09G 116

US Classification:

340747

Abstract:

A rasterizer, particularly suited for generating patterns for semiconductor masks and the like is described. An 8. times. 8 array uses RAS, CAS and WE signals in addition to the memory address for accessing the array. A state machine is used to convert the pattern data (e. g. , type of object orientation, etc. ) into accessing data with the WE generator being driven through a ROM.

US Patent:

59596066, Sep 28, 1999

Filed:

Oct 24, 1994

Appl. No.:

8/327581

Inventors:

Allan L. Goodman - Hillsboro OR
Morris H. Green - Milwauki OR
Matthew J. Jolley - Hillsboro OR
Robin L. Teitzel - Portland OR
John L. Wipfli - Hillsboro OR

Assignee:

Etec Systems, Inc. - Hayward CA

International Classification:

G09G 536

US Classification:

345133

Abstract:

A rasterizer, particularly suited for generating patterns for semiconductor masks and the like is described. An 8. times. 8 array uses RAS, CAS and WE signals in addition to the memory address for accessing the array. A state machine is used to convert the pattern data (e. g. , type of object orientation, etc. ) into accessing data with the WE generator being driven through a ROM.

US Patent:

43675247, Jan 4, 1983

Filed:

Feb 7, 1980

Appl. No.:

6/119432

Inventors:

David L. Budde - Portland OR
Stephen R. Colley - Aloha OR
Stephen L. Domenik - Portland OR
Allan L. Goodman - Hillsboro OR
James D. Howard - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 900
G06F 922
G06F 700

US Classification:

364200

Abstract:

An execution unit which is part of a general-purpose microprocessor, partitioned between two integrated circuit chips, with the execution unit on one chip and an instruction unit on another chip. The execution unit provides the interface for accessing a main memory to thereby fetch data and macroinstructions for transfer to the instruction unit when requested to do so by the instruction unit. The execution unit receives arithmetic microinstructions in order to perform various arithmetic operations, and receives access-memory microinstructions in order to develop memory references from logical addresses received from the instruction unit. Arithmetic operations are performed by a data manipulation unit which contains registers and arithmetic capability, controlled by a math sequencer. Memory references are performed by a reference-generation unit which contains base-and-length registers and an arithmetic capability to generate and check addresses for referencing an off-chip main memory, and is controlled by an access sequencer.