Allen D Chang

US Patent:

7457092, Nov 25, 2008

Filed:

Dec 7, 2005

Appl. No.:

11/296753

Inventors:

Allen Chang - Fremont CA, US
Zhinan Wei - San Jose CA, US

Assignee:

Alpha & Omega Semiconductor, LLD.

International Classification:

H02H 3/02

US Classification:

361 939, 361 57

Abstract:

A circuit and method for controlling a MOSFET based switch that includes two back-to-back FET to block current flow in the OFF state irrespective of the polarity of the voltage differential across the switch. The MOSFET based switch further has a built-in current limit function by sensing the current flow through one of the two MOSFET switches. Furthermore, the bilateral current-limited switch further includes circuitry required for controlling both P type and N type FET in either common drain or common source configuration.

US Patent:

7728655, Jun 1, 2010

Filed:

Oct 10, 2008

Appl. No.:

12/249162

Inventors:

Kevin Ng - Fremont CA, US
Zhinan Wei - San Jose CA, US
Wai-Keung Peter Cheng - Union City CA, US
Allen Chang - Fremont CA, US

Assignee:

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

International Classification:

G05F 3/02

US Classification:

327543

Abstract:

A current limiting load switch for bridging supply Vss and load with a reference voltage VRdynamically generated by a VR-generator is proposed. It includes: A pair of power FET and sense FET interconnected in split-current configuration. The FET pair develops a load voltage while limiting load current Iload to a preset maximum Imax. The FET pair is sized to draw device currents Ipower and Is with RATIO=Is/Ipower

US Patent:

7750447, Jul 6, 2010

Filed:

Jun 11, 2007

Appl. No.:

11/761313

Inventors:

Allen Chang - Fremont CA, US
Wai-Keung Peter Cheng - Union City CA, US

Assignee:

Alpha & Omega Semiconductor, Ltd - Hamilton

International Classification:

H01L 23/495
H01L 23/48
G05F 1/00

US Classification:

257676, 257777, 323222

Abstract:

A high voltage and high power boost converter is disclosed. The boost converter includes a boost converter IC and a discrete Schottky diode, both of which are co-packaged on a standard single common die pad.

US Patent:

7825508, Nov 2, 2010

Filed:

Jul 31, 2007

Appl. No.:

11/830996

Inventors:

François Hébert - San Mateo CA, US
Allen Chang - Fremont CA, US

Assignee:

Alpha Omega Semiconductor, Inc. - Sunnyvale CA

International Classification:

H01L 23/34

US Classification:

257724, 257777, 257E23003

Abstract:

A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a first die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the first die pad via an insulating die bond. Alternatively, the first die pad is grounded. The vertical MOSFET is a top drain N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the first die pad. The PRC is attached atop the first die pad via a conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.

US Patent:

8008897, Aug 30, 2011

Filed:

Jun 11, 2007

Appl. No.:

11/761301

Inventors:

Allen Chang - Fremont CA, US
Wai-Keung Peter Cheng - Union City CA, US

Assignee:

Alpha & Omega Semiconductor, Ltd - Hamilton

International Classification:

G05F 1/10
H01L 25/04

US Classification:

323222, 257777

Abstract:

A boost converter for high power and high output voltage applications includes a low voltage controller integrated circuit and a high voltage, vertical, discrete field effect transistor, both of which are packed in a single package.

US Patent:

8148817, Apr 3, 2012

Filed:

Sep 24, 2010

Appl. No.:

12/889673

Inventors:

François Hébert - San Mateo CA, US
Allen Chang - Fremont CA, US

Assignee:

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

International Classification:

H01L 23/34

US Classification:

257724, 257778, 257E23003

Abstract:

A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a first die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the first die pad via an insulating die bond. Alternatively, the first die pad is grounded. The vertical MOSFET is a top drain N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the first die pad. The PRC is attached atop the first die pad via a conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.

US Patent:

8456141, Jun 4, 2013

Filed:

Sep 1, 2011

Appl. No.:

13/224157

Inventors:

Allen Chang - Fremont CA, US
Wai-Keung Peter Cheng - Union City CA, US

Assignee:

Alpha & Omega Semiconductor, Inc. - Sunnyvale CA

International Classification:

G05F 1/10
H01L 25/04

US Classification:

323222, 257777

Abstract:

A boost converter for high power and high output voltage applications includes a low voltage controller integrated circuit and a high voltage, vertical, discrete field effect transistor, both of which are packed in a single package on separate electrically isolated die pads.

US Patent:

8504542, Aug 6, 2013

Filed:

Sep 2, 2011

Appl. No.:

13/224500

Inventors:

Allen Chang - Mountain View CA, US
John Antonio Carrino - Menlo Park CA, US

Assignee:

Palantir Technologies, Inc. - Palo Alto CA

International Classification:

G06F 7/00
G06F 17/00

US Classification:

707704

Abstract:

Techniques are provided for more efficient multi-row atomic, consistent, isolated and durable (ACID)-compliant transactions with snapshot isolation semantics (or just “multi-row transactions” for short). In some embodiments, the techniques are implemented in a computing system that includes a client application, a lightweight in-memory lease-based lock service, a multi-row transaction orchestrator, and an underlying database system. The transaction orchestrator implements a read protocol and a write protocol that provides support to the client application for carrying out multi-row transactions against the underlying database system irrespective of whether the database system itself supports multi-row transactions. The transaction orchestrator explicitly maintains transaction-level locks obtained from the lease-based lock service as part of the transaction protocol. Further, the transaction orchestrator is tolerant to lock service failure and unavailability without compromising ACID-compliance and snapshot isolation guarantees to the client application.