Alois J Gutmann

US Patent:

6379869, Apr 30, 2002

Filed:

Mar 31, 1999

Appl. No.:

09/282745

Inventors:

Uwe Paul Schroeder - Poughkeepsie NY
Gerhard Kunkel - Fishkill NY
Alois Gutmann - Poughkeepsie NY
Bruno Spuler - Wappinger Falls NY

Assignee:

Infineon Technologies AG - Munich

International Classification:

G03F 700

US Classification:

430313, 430314, 430328

Abstract:

A photoresist system is provided that is easily structurable and is suitable for deep ultraviolet range patterning. An increased etching resistance to oxygen-containing plasma is produced in a lithographically generated photoresist structure by treatment with an etch protectant. The etch protectant includes a silylating agent for chemical reaction with reactive groups of the photoresist. In an embodiment, the photoresist includes a base resin initially containing no aromatic groups. Silylating agents include silicon tetrachloride, silicon tetrafluoride, trichlorosilane, dimethylchlorosilane and hexamethyldisilazane.

US Patent:

6420101, Jul 16, 2002

Filed:

Jun 21, 2000

Appl. No.:

09/598376

Inventors:

Zhijian Lu - Poughkeepsie NY
Alan Thomas - Hughsonville NY
Alois Gutmann - Poughkeepsie NY
Kuang Jung Chen - Poughkeepsie NY
Margaret C. Lawson - Millbrook NY

Assignee:

Infineon Technologies A G - Munich
International Business Machines Corporation - Armonk NY

International Classification:

G03F 720

US Classification:

430326, 430296, 430327, 430328, 430394, 430967

Abstract:

In the exposure and development of available deep ultraviolet (DUV) sensitive photoresist it has been observed that following the standard prior art methods of exposure and development results in a high density of undesirable pieces of components of the photoresist material, Blob Defects, remaining on the semiconductor substrate (body). A method of exposing and developing the photoresist material which results in a reduced incidence of these Blob Defects consists of introducing a low level uniform flood exposure of light in addition to the commonly used exposure to patterned light, followed by standard development. The flood exposure is in the range of 5 to 50% of the dose-to-clear for a non-patterned exposure.

US Patent:

6521542, Feb 18, 2003

Filed:

Jun 14, 2000

Appl. No.:

09/593739

Inventors:

Mike Armacost - Wallkill NY
Bruno Spuler - Weixdorf, DE
Gabriela Brase - Fishkill NY
Alois Gutmann - Poughkeepsie NY

Assignee:

International Business Machines Corp. - Armonk NY
Infineon Technologies AG - Munich

International Classification:

H01L 21302

US Classification:

438712, 430326

Abstract:

A method is provided for forming a step in a layer of material. The method includes forming the layer over a substrate. A cavity is formed in a portion of an upper surface of the layer. The formed cavity is filled with a filler material to provide a substantially planar surface over the substrate. A photoresist layer is formed over the substantially planar surface over the substrate. An aperture is formed in the photoresist layer in registration with the formed cavity. The aperture exposes a portion of the filler material. The exposed portion of the filler material is removed along with a contiguous portion of the layer to form the step in the indentation. The cavity may be either a trench or a via. A âTrench Firstâ approach and a âVia Firstâ approach are described.

US Patent:

6670646, Dec 30, 2003

Filed:

Feb 11, 2002

Appl. No.:

10/074479

Inventors:

Zhijian Lu - Poughkeepsie NY
Shahid Butt - Ossining NY
Alois Gutmann - Poughkeepsie NY

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L 3300

US Classification:

257 98, 257 91

Abstract:

A mask ( ) and method for patterning a semiconductor wafer. The mask ( ) includes apertures ( ) and assist lines ( ) disposed between apertures ( ). The assist lines ( ) reduce the diffraction effects of the lithographic process, resulting in improved depth of focus and resolution of patterns on a semiconductor wafer.

US Patent:

6954002, Oct 11, 2005

Filed:

Aug 29, 2002

Appl. No.:

10/230493

Inventors:

Shoaib H. Zaidi - Poughkeepsie NY, US
Gary Williams - Mechanicsville VA, US
Alois Gutmann - Poughkeepsie NY, US

Assignee:

Infineon Technologies North America Corp. - San Jose CA

International Classification:

H01L029/06
H01L023/544

US Classification:

257797, 257622, 257623, 257618

Abstract:

A semiconductor wafer comprises a semiconductor substrate, a surface alignment mark visible on the semiconductor surface and a plurality of nanostructures on the surface of the surface alignment mark having an average pitch adapted to reduce reflectivity of the surface alignment mark in a predetermined light bandwidth.

US Patent:

7298009, Nov 20, 2007

Filed:

Feb 1, 2005

Appl. No.:

11/047928

Inventors:

Jiang Yan - Newburgh NY, US
Chun-Yung Sung - Poughkeepsie NY, US
Danny Pak-Chum Shum - Poughkeepsie NY, US
Alois Gutmann - Poughkeepsie NY, US

Assignee:

Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/12

US Classification:

257357, 257255, 257627, 257E27112

Abstract:

A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor body and a semiconductor layer overlies the insulating layer. The semiconductor layer has a second crystal orientation. A second transistor is formed in the semiconductor layer having the second crystal orientation. In the preferred embodiment, the semiconductor body is (100) silicon, the first transistor is an NMOS transistor, the semiconductor layer is (110) silicon and the second transistor is a PMOS transistor.

US Patent:

7541288, Jun 2, 2009

Filed:

Mar 8, 2007

Appl. No.:

11/683590

Inventors:

Ja-hum Ku - LaGrangeville NY, US
Alois Gutmann - Poughkeepsie NY, US
Johnny Widodo - Beacon NY, US
Dae-won Yang - Hopewell Junction NY, US

Assignee:

Samsung Electronics Co., Ltd.
International Business Machines Corporation - Armonk NY
Infineon Technologies AG
Chartered Semiconductor Manufacturing Ltd. - Singapore

International Classification:

H01L 21/311

US Classification:

438695, 438694, 438696, 438700, 438E21029

Abstract:

Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least one valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.

US Patent:

7615840, Nov 10, 2009

Filed:

Jun 21, 2007

Appl. No.:

11/766234

Inventors:

Roland Hampp - Poughkeepsie NY, US
Alois Gutmann - Poughkeepsie NY, US
Jin-Ping Han - Fishkill NY, US
O Sung Kwon - Wappingers Falls NY, US

Assignee:

Infineon Technologies AG - Neubiberg

International Classification:

H01L 29/06

US Classification:

257506, 257374, 257E29018

Abstract:

A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.