Amit A Mittra from 58 Murica Aisle, Irvine, CA 92614, age 48

Name / Title

Company / Classification

Phones & Addresses

Amit Mittra
Chief Technology Officer, President

HIMAX IMAGING CORP
Whol Computers/Peripherals

36 Discovery SUITE 270, Irvine, CA 92618
(949)5859838

Resumes

Chief Technology Officer

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Location:

Irvine, CA

Industry:

Semiconductors

Work:

Himax Imaging
CTO
Biomorphic Feb 1999 - Dec 2006
Design Engineer

Education:

Indian Institute of Technology, Delhi
Bachelor of Technology (B.Tech.), Electrical and Electronics Engineering USC
Master's degree, Electrical and Electronics Engineering

Skills:

Cmos
Semiconductors
Soc
Asic
Cmos Image Sensors For Various Applications
Analog Circuit Design
Mixed Signal
Sensors
Image Processing
Semiconductor Industry

Languages:

Hindi
English

Amit Mittra

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Us Patents

System And Method For Automatic Exposure Control And White Balancing For Cmos Sensors
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US Patent:

7728897, Jun 1, 2010
Filed:

May 10, 2006
Appl. No.:

11/382627
Inventors:

Mihail M. Milkov - Thousand Oaks CA, US
David Standley - Westlake Village CA, US
Amit Mittra - Westlake Village CA, US
Assignee:

Biomorphic VLSI, Inc. - Westlake Village CA
International Classification:

H04N 3/14
H04N 5/335
H01L 27/00
US Classification:

348308, 348294, 2502081
Abstract:

A system and method for averaging incident light on plural pixels using a CMOS sensor is provided. The process includes resetting all pixels in a given region during a reset phase; and reading a voltage of a floating reset node as a function of time during a measurement phase. During the reset phase, an access select signal and a reset voltage are both high. The measurement phase begins when the access select signal is low and the reset voltage is still high. The system and method may be used to perform automatic exposure control and automatic white balancing operations.

Multi-Phase Black Level Calibration Method And System
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US Patent:

8218038, Jul 10, 2012
Filed:

Dec 11, 2009
Appl. No.:

12/635711
Inventors:

Nguyen Dong - Irvine CA, US
Amit Mittra - Irvine CA, US
Ray-Chi Chang - Irvine CA, US
Assignee:

Himax Imaging, Inc. - Tainan
International Classification:

H04N 9/64
US Classification:

348243
Abstract:

Multi-phase black level calibration (BLC) methods and systems are generally disclosed. According to one embodiment of the present invention, an image sensor comprises a pixel sensor array, a timing generator, and a front-end processing block. The front-end processing block also includes a first summing junction, a first BLC block, and a second BLC block. According to a first timing signal from the timing generator, the first BLC block is configured to iteratively generate a first calibration signal in a first phase based on a first set of adjusted black level signals associated with a first set of black pixels, a changing accumulator step, and a predetermined condition associated with a first target black level. According to a second timing signal from the timing generator, the second BLC block is configured to generate a second calibration signal for a second summing junction to apply to an image signal associated with one or more active pixels in the frame in a second phase.

Signal Chain Of An Imaging System
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US Patent:

8253827, Aug 28, 2012
Filed:

Sep 8, 2009
Appl. No.:

12/555654
Inventors:

Chih-Min Liu - Tainan, TW
Amit Mittra - Irvine CA, US
Chi-Shao Lin - Tainan, TW
Assignee:

Himax Imaging, Inc. - Grand Cayman
International Classification:

H04N 9/64
H04N 5/235
H04N 5/228
US Classification:

348243, 3482211, 3482221
Abstract:

A signal chain of an imaging system is disclosed. The system includes three circuit stages. The first circuit stage includes a programmable gain amplifier (PGA) and a black level compensation (BLC) circuit that form a BLC loop. The second circuit stage includes an analog-to-digital converter (ADC), where a dark signal offset is added at an input of the ADC. The third circuit stage includes a digital gain circuit and a digital loop that makes a final output of the imaging system settle on a target level in the BLC mode.

Black Level Calibration Method And System
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US Patent:

8564697, Oct 22, 2013
Filed:

Oct 21, 2009
Appl. No.:

12/582715
Inventors:

Nguyen Dong - Irvine CA, US
Amit Mittra - Irvine CA, US
Chi-Shao Lin - Irvine CA, US
Assignee:

Himax Imaging, Inc. - Grand Cayman
International Classification:

H04N 9/64
US Classification:

348243, 348187
Abstract:

Black level calibration methods and systems are generally disclosed. According to one embodiment of the present invention, a method of calibrating a black level signal in a frame includes performing an iteration of averaging a first set of digital values corresponding to a first set of adjusted black level signals associated with a first set of black pixels of the frame, determining whether an average value based on the first set of digital values has reached a target black level, determining a calibration offset based on a difference between the average value and the target black level and an accumulator step, converting the calibration offset to an analog signal, generating a calibration signal based on the analog signal for a second set of black pixels of the frame, and repeating the iteration for the frame until a predetermined condition is determined to have been met.

Integrator Ramp Generator With Dac And Switched Capacitors
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US Patent:

8614639, Dec 24, 2013
Filed:

Aug 24, 2012
Appl. No.:

13/593520
Inventors:

Ping Hung Yin - Irvine CA, US
Satya Narayan Mishra - Irvine CA, US
Amit Mittra - Irvine CA, US
Assignee:

Himax Imaging, Inc. - Grand Cayman
International Classification:

H03M 1/56
US Classification:

341169, 341155, 341144
Abstract:

A ramp generator includes a digital-to-analog converter (DAC), a sampling capacitor, an integrator circuit, a polarity reversing switch selectively coupling first and second outputs of the DAC to a first side of the sampling capacitor, a first switch coupling a second side of the sampling capacitor to a reference voltage source, and a second switch coupling the second side of the sampling capacitor to an input of the integrator circuit.

System And Method For Automatic Exposure Control And White Balancing For Cmos Sensors
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US Patent:

20040141074, Jul 22, 2004
Filed:

Jan 17, 2003
Appl. No.:

10/346235
Inventors:

Mihail Milkov - Thousand Oaks CA, US
David Standley - Westlake Village CA, US
Amit Mittra - Westlake Village CA, US
International Classification:

H04N005/335
US Classification:

348/296000
Abstract:

A system and method for averaging incident light on plural pixels using a CMOS sensor is provided. The process includes resetting all pixels in a given region during a reset phase; and reading a voltage of a floating reset node as a function of time during a measurement phase. During the reset phase, an access select signal and a reset voltage are both high. The measurement phase begins when the access select signal is low and the reset voltage is still high. The system and method may be used to perform automatic exposure control and automatic white balancing operations.

Method And Circuit For Driving Active Pixels In A Cmos Imager Device
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US Patent:

20090295965, Dec 3, 2009
Filed:

May 30, 2008
Appl. No.:

12/129900
Inventors:

Desmond Yu Hin Cheung - Irvine CA, US
Amit Mittra - Irvine CA, US
Chi-Shao Lin - Hsinchu, TW
Assignee:

HIMAX IMAGING, INC. - Grand Cayman
International Classification:

H04N 5/335
H01L 27/146
US Classification:

348308, 257292, 348E05091, 257E27133
Abstract:

One embodiment of the present invention describes a pixel circuit that comprises at least one photodiode, a first transistor coupled between the photodiode and a floating diffusion node, a second transistor coupled between the floating diffusion node and a modifiable driving voltage signal, and a third transistor having a gate coupled to the floating diffusion node, a source coupled to a signal output, and a drain coupled to a constant voltage. Another embodiment of the present invention provides a method for driving the pixel circuit, which comprises resetting the photodiode and the floating diffusion node, exposing the photodiode to light to accumulate charges, selecting the pixel circuit by switching the driving voltage signal from a first voltage level to a second voltage level, retrieving a reference voltage from the selected pixel circuit, and retrieving an image signal from the selected pixel circuit corresponding to the accumulated charges.

Ultra Low Readout Noise Architecture
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US Patent:

20150136956, May 21, 2015
Filed:

Jan 29, 2015
Appl. No.:

14/608205
Inventors:

- Grand Cayman, KY
Amit MITTRA - Irvine CA, US
Kaveh MOAZZAMI - Irvine CA, US
Kwangoh KIM - Irvine CA, US
Satya Narayan MISHRA - Irvine CA, US
International Classification:

H04N 5/378
US Classification:

2502081
Abstract:

A method to read out pixels includes reading a first pixel by resetting a first photodetector, integrating the first photodetector after resetting the first photodetector, resetting a first floating diffusion node coupled to the first photodetector and a second floating diffusion node coupled to a second photodetector, transferring charge from the first photodetector to the first floating diffusion node, comparing a first signal at the first floating diffusion node and a second signal at the second floating diffusion node and generating a first signal to latch a first counter value when the first signal is less than the second signal, incrementing the first signal and decrementing the second signal, and comparing the first signal and the second signal and generating a second signal to latch a second counter value when the first signal is greater than the second signal, wherein the difference between the second counter value and the first counter value indicates a first pixel level.