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Amit Nayak

age ~47

from Atlanta, GA

Amit Nayak Phones & Addresses

  • 2986 Rivergreen Ln SE APT 21, Atlanta, GA 30339
  • Torrance, CA
  • Newark, DE
  • Auburn Hills, MI
  • 2986 Rivergreen Ln SE, Atlanta, GA 30339

Work

  • Position:
    Medical Professional

Education

  • Degree:
    Associate degree or higher

Resumes

Amit Nayak Photo 1

Finance

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Location:
United States
Industry:
Financial Services
Amit Nayak Photo 2

Senior Project Manager At Siemens Industry Usa

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Location:
Atlanta, GA
Industry:
Electrical/Electronic Manufacturing
Work:
Siemens Industry Inc. since Oct 2009
Sr. Software Engineer
Education:
University of Delaware 1999 - 2002
Masters, Master of Science In Electrical Engineering, Computer Engineering
University of Mumbai 1995 - 1999
Bachelors, Bachelor of Science, Electronics Engineering
Kendriya Vidyalaya
Skills:
Embedded Systems
Embedded Software
Firmware
Testing
Software Design
Digital Signal Processors
Integration
Low Level Programming
Software Development
Software Engineering
Digital Hardware
Asic
Hardware
Pcb Design
Amit Nayak Photo 3

Amit Nayak

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Location:
United States
Amit Nayak Photo 4

Sr. Software Engineer At Siemens Industry Inc.

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Location:
Greater Atlanta Area
Industry:
Electrical/Electronic Manufacturing

Us Patents

  • Multifunctional Residential Circuit Breaker

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  • US Patent:
    8023235, Sep 20, 2011
  • Filed:
    Mar 17, 2009
  • Appl. No.:
    12/405340
  • Inventors:
    Mario Bilac - Lawrenceville GA, US
    Carlos Restrepo - Atlanta GA, US
    Hugh T. Kinsel - Sugar Hill GA, US
    Amit Nayak - Atlanta GA, US
  • Assignee:
    Siemens Industry, Inc. - Alpharetta GA
  • International Classification:
    H02H 3/00
  • US Classification:
    361 42, 361 931, 361 94, 324500
  • Abstract:
    An electrical fault detection device for use in a branch of a power circuit that utilizes signals from an AC line current sensor coupled to an electrical distribution line having a primary and neutral lines, a line high-frequency sensor coupled to the electrical distribution line, a differential current sensor coupled to the primary and neutral lines, and a ground fault current sensor coupled to the primary and neutral lines. A signal conditioner receives the signals outputted by AC current line current sensor, the line high frequency sensor, the differential current sensor and the ground fault current sensor and generates a signal indicative of the load current associated with a branch of the power circuit. Output of the signal conditioner is sampled and processed by a processing resource. The processing resource has stored therein data representing a plurality of time-versus-current curves that define a plurality of regions in which tripping may or may not occur.
  • Visual Indication Of Fault Status, Storage And Clearance In An Arc Fault Circuit Interrupter (Afci)

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  • US Patent:
    8184011, May 22, 2012
  • Filed:
    Oct 6, 2009
  • Appl. No.:
    12/574449
  • Inventors:
    Amit Nayak - Atlanta GA, US
    Carlos Restrepo - Atlanta GA, US
    Brian Timothy McCoy - Lawrenceville GA, US
  • Assignee:
    Siemens Industry, Inc. - Alpharetta GA
  • International Classification:
    G08B 21/00
    H02H 7/00
  • US Classification:
    340657, 340662, 340664, 340650, 361 42
  • Abstract:
    An arc fault detector includes a means for repeatedly measuring an elapsed time. The arc fault detector also includes at least one means to perform arc detection at each repeated elapsed time. Means for initiating a tripping mechanism is activated after the elapsed time. When a fault occurs, means for generating at least one fault code is activated. The fault code is stored in at least one non-volatile memory. The fault code is selected from a group consisting of an arc fault interrupt code, a ground fault interrupt code, and a push-to-test interrupt code. The arc fault detector includes at least one means to display the fault code such as at least one LED. At least a first LED indicates an arc fault interrupt code and at least a second LED indicates a ground fault interrupt code. At least a third LED indicates a push-to-test interrupt code.
  • Systems And Methods For Arc Fault Detection

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  • US Patent:
    20080106832, May 8, 2008
  • Filed:
    Oct 30, 2007
  • Appl. No.:
    11/978969
  • Inventors:
    Carlos Restrepo - Beaverton OR, US
    Peter Staley - Kings Park NY, US
    Amit Nayak - Atlanta GA, US
    Vaske Mikani - Atlanta GA, US
    Hugh Kinsel - Sugar Hill GA, US
  • International Classification:
    H02H 3/16
  • US Classification:
    361042000
  • Abstract:
    In accordance with one aspect the present disclosure is directed toward a method for detecting arc faults on a power line. The method may include monitoring power signals associated with a power line and filtering the power signals to produce a high frequency signal and a low frequency signal. A mask signal may generated based on the low frequency signal, and the high frequency signal may be analyzed to extract a broadband portion of the high frequency signal. A fault counter may be incremented if the magnitude of the broadband portion is approximately greater than a first threshold level. A fault counter may be decremented if the magnitude of the broadband portion is approximately less than the first threshold level. A trip signal is provided to a switching device associated with the power line if the fault counter exceeds a predetermined fault limit.
  • Arc Fault Circuit Detection Methods, Systems, And Apparatus Including Delay

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  • US Patent:
    20110249370, Oct 13, 2011
  • Filed:
    Apr 6, 2011
  • Appl. No.:
    13/081146
  • Inventors:
    Amit Nayak - Atlanta GA, US
    Hugh T. Kinsel - Sugar Hill GA, US
  • Assignee:
    SIEMENS INDUSTRY, INC. - Alpharetta GA
  • International Classification:
    H02H 3/08
  • US Classification:
    361 42
  • Abstract:
    In one aspect, a method of electrical arc fault detection when high frequency (e.g., RF noise) is present is disclosed. The method includes determining if first arcing criterion is met, determining if delay criterion is met, implementing a delay for a delay period if the delay criterion is met, and determining if second arcing criterion is met. If the second arcing criterion is met, then a trip signal may be sent to trip the circuit breaker. In another aspect, the method includes determining if first arcing criterion is met, starting delay period if the first arcing criterion is met, determining if delay criterion is met, and if the delay criterion is met, determining if second arcing criterion is met. An arc fault detection apparatus adapted to carry out the methods, and systems including the arc fault detection apparatus are disclosed, as are various other aspects.
  • Methods, Systems, And Apparatus And For Detecting Parallel Electrical Arc Faults

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  • US Patent:
    20120229939, Sep 13, 2012
  • Filed:
    Mar 11, 2011
  • Appl. No.:
    13/045751
  • Inventors:
    Vaske Mikani - Senoia GA, US
    Amit Nayak - Atlanta GA, US
  • Assignee:
    SIEMENS INDUSTRY, INC. - Alpharetta GA
  • International Classification:
    H02H 9/02
    H02H 3/02
  • US Classification:
    361 55
  • Abstract:
    In one aspect, a method for detecting arc faults with a dynamically-changeable slope threshold is disclosed. The method may include monitoring a current waveform to determine a peak amplitude of a half cycle and a slope at a zero crossing of a half cycle. An arc fault counter may be incremented if the maximum amplitude of the half cycle and the slope at a zero crossing are greater than a preset magnitude threshold level and the dynamically-changeable slope threshold, respectively. In another aspect, a decay of the amplitude of a predetermined number of half cycles of the current waveform is measured and an arc counter is not incremented, even if the conditions would otherwise indicate an arc counter increment, when the decay is above a decay threshold for greater than a predetermined number of half cycles. An arc fault detection apparatus adapted to carry out the methods, and systems including the arc fault detection apparatus are disclosed, as are various other aspects.

Myspace

Amit Nayak Photo 5

amit Nayak

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Locality:
Orissa, India
Gender:
Male
Birthday:
1948
Amit Nayak Photo 6

Amit Nayak

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Locality:
India
Gender:
Male
Birthday:
1934
Amit Nayak Photo 7

Amit Nayak

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Locality:
India
Gender:
Male
Birthday:
1947
Amit Nayak Photo 8

Amit Nayak

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Gender:
Male
Birthday:
1949

Googleplus

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Amit Nayak

Work:
Amit nayak - Lecturer of electronics n telecommunication engineering (2011)
Education:
ABIT, CUTTACK - Btech in Electronics N telecommunication Engineering
Tagline:
Cooly hot
Amit Nayak Photo 10

Amit Nayak

Work:
Accenture
Education:
Msrit
Amit Nayak Photo 11

Amit Nayak

Work:
BIOWIN CHEMICAL (P) LTD. - A.S.M.
Amit Nayak Photo 12

Amit Nayak

Education:
University of Pune
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Amit Nayak

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Amit Nayak

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Amit Nayak

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Amit Nayak

Plaxo

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Amit Nayak

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Youtube

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Amit Nayak Post Fight at Live at Landsdowne III

"I definately want to fight again. There's a lot in this fight that I ...

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    1m 24s

Classmates

Amit Nayak Photo 18

Amit Nayak (Amit)

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Schools:
Cambridge Academy Cambridge MA 2003-2007
Community:
Doreen Jenkins, Stephen Harrod

Facebook

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Amit Nayak

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Nayak Amit

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Amit Nayak Photo 21

Amit G Nayak

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Amit Nayak Photo 22

Amit Kumar Nayak

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Amit Nayak Photo 23

Amit Kumar Nayak

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Amit Nayak Photo 24

Amit Kumar Nayak

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Amit Nayak Photo 25

Amit Kumar Nayak

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Amit Nayak Photo 26

Amit Kumar Nayak

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