Amit Raj Pandey

US Patent:

20120062283, Mar 15, 2012

Filed:

Sep 9, 2010

Appl. No.:

12/878693

Inventors:

Bill K. Kwan - Austin TX, US
Atchyuth K. Gorti - Austin TX, US
Amit Raj Pandey - Austin TX, US
Venkat K. Kuchipudi - Austin TX, US
Aditya Jagirdar - Austin TX, US

International Classification:

H03L 7/00

US Classification:

327143, 327198

Abstract:

Scan-based reset utilizes already existing design-for-test scan chains to reset control and logic circuitry upon reset conditions, such as power-up reset. Such utilization eliminates the need for expensive, high fan-out reset trees and per scan cell reset control logic, thus reducing chip area and power consumption. Additional power savings is achieved by controlling clock frequency during reset conditions. Limiting scan cell chain length and providing multiple chains reduces reset latency.

US Patent:

20120124424, May 17, 2012

Filed:

Nov 17, 2010

Appl. No.:

12/948443

Inventors:

Atchyuth K. Gorti - Austin TX, US
Salih Hamid - Austin TX, US
Amit Pandey - Austin TX, US
William Yang - Austin TX, US

International Classification:

G06F 11/26

US Classification:

714 27, 714E11159

Abstract:

A method and apparatus to improve the efficiency of debugging a processor is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes receiving a first test data, which identifies a state of a state machine, wherein the state machine performs reset and initialization operations for a processor. The method also includes halting the state machine in the state identified by the first test data upon reaching the state.

US Patent:

7568134, Jul 28, 2009

Filed:

Feb 2, 2004

Appl. No.:

10/770170

Inventors:

Amit Raj Pandey - Austin TX, US
Peggy A. Nissen - Cupertino CA, US
Shridhar G. Bendi - Karnataka, IN

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 29/00
G01R 31/28
G06F 17/10

US Classification:

714718, 714738, 703 2

Abstract:

A model of the memory device is provided, including a memory array model having a plurality of memory array model locations, and a plurality of decoder models, each associated with a memory array model location. Each memory array model location includes a first data set accessed with the input to that memory array model location in a first state, and a second data set accessed with the input to that memory array model location in a second state. The memory device model is provided to an automatic test pattern generation (ATPG) tool, and a test pattern is generated based on the memory device model.

US Patent:

20220358196, Nov 10, 2022

Filed:

May 4, 2021

Appl. No.:

17/307469

Inventors:

- Austin TX, US
Amit PANDEY - Austin TX, US

International Classification:

G06F 21/32
G06F 21/40
G06N 3/02

Abstract:

The present invention relates to a method of fusing at least two different candidate lists into a single candidate list, said at least two different candidate lists being generated by matching biometric data captured from an individual to be identified and biometric data enrolled from candidates to calculate match scores of candidates and ranking said match scores, the method comprising steps of:

Address:

10620 Redmond Rd, Austin, TX 78739

VIN:

JTDKB20U577548546

Make:

TOYOTA

Model:

PRIUS

Year:

2007