Ana Rosa Arias

US Patent:

7784173, Aug 31, 2010

Filed:

Dec 27, 2005

Appl. No.:

11/318926

Inventors:

Michal V. Wolkin - Los Altos CA, US
Ana C. Arias - San Carlos CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H05B 3/00

US Classification:

29611, 29825, 29829, 374208, 374E17001

Abstract:

A layered structure is produced on a support structure's surface. The layered structure can include a component that responds electrically to thermal signals, such as a thermistor, and can also include a layer part that has a printed patterned artifact such as an uneven boundary or an alignment. A layered structure can be produced by depositing a layer of material, printing a mask, and removing the exposed part of the layer.

US Patent:

7816146, Oct 19, 2010

Filed:

Dec 27, 2005

Appl. No.:

11/318967

Inventors:

Michal V. Wolkin - Los Altos CA, US
Ana C. Arias - San Carlos CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

G01N 25/20

US Classification:

436147, 422 51, 422 681

Abstract:

A passive electronic device includes layers of a layered structure on a support surface. The device can include a first layer part that includes electrically conductive or semiconductive material and that has a contact surface. The device can also include second layer parts that include electrically conductive material and are in electrical contact with the contact surface, with a subset electrically connectible to external circuitry. At least one of the parts of the two layers can be produced by a printing operation or can include a printed patterned artifact such as an uneven boundary or an alignment. The printing operation can be direct printing or printing of a mask for etching or liftoff or both. The device could, for example, be a resistive device, such as a device with resistance varying in response to non-electrical stimuli, or a conductive device, such as with a contact pad for a pogo pin.

US Patent:

8053818, Nov 8, 2011

Filed:

Dec 18, 2009

Appl. No.:

12/642132

Inventors:

Sanjiv Sambandan - Sunnyvale CA, US
Ana Claudia Arias - Los Gatos CA, US
Gregory Lewis Whiting - Menlo Park CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 27/148
H01L 21/3205

US Classification:

257250, 438588

Abstract:

A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.

US Patent:

8158973, Apr 17, 2012

Filed:

Oct 28, 2009

Appl. No.:

12/607890

Inventors:

Tse Nga Ng - Mountain View CA, US
Ana C. Arias - Los Gatos CA, US
Sanjiv Sambandan - Sunnyvale CA, US
Robert A. Street - Palo Alto CA, US
Jurgen H. Daniel - San Francisco CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 51/10

US Classification:

257 40, 257295, 257E51006

Abstract:

An organic non-volatile memory array including multiple pixels and associated signal lines that are disposed on and between a substrate, a single ferroelectric dielectric layer, and a single organic dielectric layer, where each pixel includes a ferroelectric field-effect transistor (FeFET) and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of a selected pixel without disturbing the data stored in adjacent pixels. Analog data storage in the FeFET array is also introduced that does not require analog-to-digital conversion of the stored data.

US Patent:

8164122, Apr 24, 2012

Filed:

Sep 21, 2011

Appl. No.:

13/239078

Inventors:

Sanjiv Sambandan - Sunnyvale CA, US
Ana Claudia Arias - Los Gatos CA, US
Gregory Lewis Whiting - Menlo Park CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 27/148
H01L 21/3205

US Classification:

257250, 438588

Abstract:

A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.

US Patent:

8268725, Sep 18, 2012

Filed:

Oct 7, 2010

Appl. No.:

12/900417

Inventors:

Sanjiv Sambandan - Sunnyvale CA, US
Robert A. Street - Palo Alto CA, US
Ana Claudia Arias - Los Gatos CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 21/288

US Classification:

438679, 438674, 438686, 427 995, 427125, 427256, 257E21174, 977762, 977857, 977932

Abstract:

A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e. g. , TFTs for large-area electronic devices.

US Patent:

8288799, Oct 16, 2012

Filed:

Mar 21, 2012

Appl. No.:

13/426518

Inventors:

Sanjiv Sambandan - Sunnyvale CA, US
Ana Claudia Arias - Los Gatos CA, US
Gregory Lewis Whiting - Menlo Park CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 27/148
H01L 21/3205

US Classification:

257250, 438588

Abstract:

A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.

US Patent:

8637138, Jan 28, 2014

Filed:

Dec 27, 2005

Appl. No.:

11/318975

Inventors:

Michal V. Wolkin - Los Altos CA, US
Ana C. Arias - San Carlos CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

B41M 5/52
G01K 17/00
G01K 7/24

US Classification:

4281951, 374 31, 374183

Abstract:

A thin substrate has a layered structure on one surface, and can also have a layered structure on the other. Each layered structure can include a part of at least one patterned layer that, if patterned by photolithography, would frequently result in damage to the substrate due to fragility. For example, the substrate could be a 3 mil (76. 2 μm) or thinner polyimide film and one patterned layer could be a semiconductor material such as vanadium oxide, while another could be metal in electrical contact with semiconductor material. The layer part, however, can be patterned by a printing operation or can include a printed patterned artifact such as an uneven boundary or an alignment. The printing operation can be direct printing or printing of a mask for etching or liftoff or both. The layered structure can include an array of cells, each with layer parts on each substrate surface.