Ana Daysi Arias

US Patent:

7300861, Nov 27, 2007

Filed:

Jun 24, 2004

Appl. No.:

10/875480

Inventors:

Ana C. Arias - San Carlos CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 21/44

US Classification:

438597, 438 99, 438197, 257E21041, 257E21575

Abstract:

An improved method of interconnecting electronic devices is described. In the method a blended material for forming a conducting layer and an insulating layer are deposited between a contact of a first electronic device and a second electronic device. The blended material leads to formation of a conductor overlayed by an insulator such that after formation, the conductor is capable of carrying current from the first electronic device to the second electronic device and the insulator forms a protective layer over the conductor.

US Patent:

7351606, Apr 1, 2008

Filed:

Jun 24, 2004

Appl. No.:

10/876229

Inventors:

Ana C. Arias - San Carlos CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 51/40

US Classification:

438 99, 257E51005

Abstract:

An improved method of forming a semiconducting polymer layer protected by an insulating polymer layer is described. In the method, a material for forming a semiconducting polymer and an insulating polymer are dissolved in a solvent. The blended solution is deposited on a substrate where the semiconducting polymer and insulating polymer segregate. Upon evaporation of the solvent, the semiconducting material forms the active region of a TFT and the insulating polymer minimizes the exposure of the semiconducting polymer to air.

US Patent:

7459400, Dec 2, 2008

Filed:

Jul 18, 2005

Appl. No.:

11/184304

Inventors:

Ana C. Arias - San Carlos CA, US
Rene A. Lujan - Sunnyvale CA, US
William S. Wong - San Carlos CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 21/311

US Classification:

438695, 438149

Abstract:

A patterned integrated circuit structure defining a gap or via is fabricated solely by digital printing and bulk processing. A sacrificial lift-off pattern is printed or otherwise formed over a substrate, and then covered by a blanket layer. A mask is then formed, e. g. , by printing a wax pattern that covers a region of the blanket layer corresponding to the desired patterned structure, and overlaps the lift-off pattern. Exposed portions of the blanket layer are then removed, e. g. , by wet etching. The printed mask and the lift-off pattern are then removed using a lift-off process that also removes any remaining portions of the blanket layer formed over the lift-off pattern. A thin-film transistor includes patterned source/drain structures that are self-aligned to an underlying gate structure by forming a photoresist lift-off pattern that is exposed and developed by a back-exposure process using the gate structure as a mask.

US Patent:

7514114, Apr 7, 2009

Filed:

Sep 1, 2005

Appl. No.:

11/218416

Inventors:

William S. Wong - San Carlos CA, US
Steven E. Ready - Mountain View CA, US
Ana Claudia Arias - San Carlos CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

C23C 16/52
B05D 5/12

US Classification:

427 8, 427 58, 347 14, 347 43, 347 54

Abstract:

A digital lithography system prints a large-area electronic device by dividing the overall device printing process into a series of discrete feature printing sub-processes, where each feature printing sub-process involves printing both a predetermined portion (feature) of the device in a designated substrate area, and an associated test pattern in a designated test area that is remote from the feature. At the end of each feature printing sub-process, the test pattern is analyzed, e. g. , using a camera and associated imaging system, to verify that the test pattern has been successfully printed. A primary ejector is used until an unsuccessfully printed test pattern is detected, at which time a secondary (reserve) ejector replaces the primary ejector and reprints the feature associated with the defective test pattern. When multiple printheads are used in parallel, analysis of the test pattern is used to efficiently identify the location of a defective ejector.

US Patent:

7524768, Apr 28, 2009

Filed:

Mar 24, 2006

Appl. No.:

11/388718

Inventors:

Eugene M. Chow - Freemont CA, US
William S. Wong - San Carlos CA, US
Michael Chabinyc - Burlingame CA, US
Jeng Ping Lu - San Jose CA, US
Ana Claudia Arias - San Carlos CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 21/302

US Classification:

438706, 438725, 216 74

Abstract:

A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.

US Patent:

7566899, Jul 28, 2009

Filed:

Dec 21, 2005

Appl. No.:

11/316551

Inventors:

Michael L. Chabinyc - Burlingame CA, US
Rene A Lujan - Sunnyvale CA, US
Ana Claudia Arias - San Carlos CA, US
Jackson H. Ho - Palo Alto CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 51/10
G02F 1/1345

US Classification:

257 40, 257448, 257E51006, 349151

Abstract:

A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and drain contacts and the address lines are fabricated using a multi-layer structure including a relatively thick base portion formed of a relatively inexpensive metal (e. g. , aluminum or copper), and a relatively thin contact layer formed of a high work function, low oxidation metal (e. g. , gold) that exhibits good electrical contact to the organic semiconductor, is formed opposite at least one external surface of the base, and is located at least partially in an interface region where the organic semiconductor contacts an underlying dielectric layer.

US Patent:

7576000, Aug 18, 2009

Filed:

Dec 22, 2006

Appl. No.:

11/615229

Inventors:

Jurgen H. Daniel - San Francisco CA, US
Ana C. Arias - San Carlos CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 21/4763

US Classification:

438637, 438780, 438781, 257E23134

Abstract:

A method forms a first active electronic layer, prints an array of pillars on the first active electronic layer, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the curable polymer with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer. Another method provides a substrate having selected areas, prints an array of pillars on the substrate, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer corresponding to the selected areas. Another method forms a first active electronic layer on a substrate, prints an array of conductive pillars on the active electronic layer on a substrate, dispenses a curable polymer on the array of conductive pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from the upper surfaces of the conductive pillars, curing the curable polymer to produce a hardened polymer, and forms a second active electronic layer on the hardened polymer such that the second active electronic layer is in electrical connection with the first active electronic layer through the conductive pillars.

US Patent:

7615483, Nov 10, 2009

Filed:

Dec 22, 2006

Appl. No.:

11/644250

Inventors:

Jurgen H. Daniel - San Francisco CA, US
Ana C. Arias - San Carlos CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

H01L 21/4763

US Classification:

438637, 977775, 977776

Abstract:

A method of forming vias and pillars using printed masks is described. The printed masks are typically made from droplets that include suspended metal nanoparticles. The use of the same metal nanoparticle solution in both the mask formation and the subsequent formation of conducting structures simplifies the fabrication process.