Andrei Papou

US Patent:

7525323, Apr 28, 2009

Filed:

Jan 16, 2007

Appl. No.:

11/623531

Inventors:

Peter J. Hopper - San Jose CA, US
Kyuwoon Hwang - Palo Alto CA, US
Peter I. Smeys - Mountain View CA, US
Andrei Papou - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G01R 27/08
G01R 33/12
G01R 31/26

US Classification:

324691, 324713, 324719

Abstract:

A method for determining consistency of a permeability of a ferromagnetic material in integrated circuits in which a test strip of the subject ferromagnetic material is included for testing with an impedance measurement instrument, such as an inductance-capacitance-resistance (LCR) meter, with which the resistance of the strip of ferromagnetic material over a range of measurement signal frequencies is determined based upon the measured impedance values. The measured impedance values, measurement signal frequencies and selected permeability values are then used in numerical simulations to produce multiple resistance versus frequency curves each of which corresponds to one of the selected permeability values.

US Patent:

7584533, Sep 8, 2009

Filed:

Oct 10, 2007

Appl. No.:

11/973861

Inventors:

Peter Smeys - Mountain View CA, US
Peter Johnson - Sunnyvale CA, US
Andrei Papou - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01F 3/00
H01F 41/02

US Classification:

29604, 296021, 29605, 29606, 29840, 228175, 22818022, 228219, 336110, 336175, 336178, 336184, 336214, 363 17, 363 48, 363 58

Abstract:

A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis can be enhanced by electroplating in an applied magnetic field parallel to the easy axis.

US Patent:

7652348, Jan 26, 2010

Filed:

Jul 27, 2006

Appl. No.:

11/495143

Inventors:

Peter J. Hopper - San Jose CA, US
Peter Johnson - Sunnyvale CA, US
Kyuwoon Hwang - Palo Alto CA, US
Andrei Papou - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/20

US Classification:

257531, 257E21022, 438381

Abstract:

An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer and are in electrical contact with a switching node of the power circuitry on each die respectively. The inductors are fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer for each die on the wafer. An insulating layer and then inductor coils are then formed over the plurality of magnetic core inductor members over each die. A layer of magnetic paste is also optionally provided over each inductor coil to further increase inductance.

US Patent:

7755463, Jul 13, 2010

Filed:

Oct 13, 2008

Appl. No.:

12/250382

Inventors:

Peter J. Hopper - San Jose CA, US
Peter Johnson - Sunnyvale CA, US
Peter Smeys - Mountain View CA, US
Andrei Papou - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01F 5/00
H01F 27/28
H01F 21/06
H01F 27/30
H01F 27/24
H02M 1/00
G05F 1/00

US Classification:

336200, 336223, 336232, 336131, 336170, 336186, 336196, 336216, 336221, 336222, 363147, 323272

Abstract:

The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways.

US Patent:

7829425, Nov 9, 2010

Filed:

Aug 15, 2006

Appl. No.:

11/504972

Inventors:

Peter J. Hopper - San Jose CA, US
Peter Johnson - Sunnyvale CA, US
Kyuwoon Hwang - Palo Alto CA, US
Andrei Papou - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/20

US Classification:

438381, 257531, 257E21022

Abstract:

An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

US Patent:

7897472, Mar 1, 2011

Filed:

Nov 23, 2009

Appl. No.:

12/624259

Inventors:

Peter J. Hopper - San Jose CA, US
Peter Johnson - Sunnyvale CA, US
Kyuwoon Hwang - Palo Alto CA, US
Andrei Papou - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 21/20

US Classification:

438381, 257531, 257E21022

Abstract:

Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils.

US Patent:

7936246, May 3, 2011

Filed:

Oct 9, 2007

Appl. No.:

11/973536

Inventors:

Peter J. Hopper - San Jose CA, US
Peter Smeys - Mountain View CA, US
Andrei Papou - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01F 27/24

US Classification:

336212, 336200, 336221, 336223

Abstract:

Saturation of nonlinear ferromagnetic core material for on-chip inductors for high current applications is significantly reduced by providing a core design wherein magnetic flux does not form a closed loop, but rather splits into multiple sub-fluxes that are directed to cancel each other. The design enables high on-chip inductance for high current power applications.

US Patent:

8314676, Nov 20, 2012

Filed:

May 2, 2011

Appl. No.:

13/098656

Inventors:

Peter Smeys - San Jose CA, US
Andrei Papou - San Jose CA, US
Peter Johnson - Sunnyvale CA, US
Anuraag Mohan - Fremont CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01F 5/00
H01F 7/06
H01L 27/08

US Classification:

336200, 257531, 296021

Abstract:

A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween.