Andrew M Anderson

US Patent:

6345009, Feb 5, 2002

Filed:

Sep 8, 2000

Appl. No.:

09/658465

Inventors:

Ely K. Tsern - Los Altos CA
Richard M. Barth - Palo Alto CA
Paul G. Davis - San Jose CA
Craig E. Hampel - San Jose CA
Thomas J. Holman - Portland OR
Andrew V. Anderson - Portland OR

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G11C 700

US Classification:

365222, 365120, 711106

Abstract:

A memory system includes a set of memory devices. An interconnect structure links the set of memory devices to one another. A memory controller is connected to the interconnect structure. The memory controller is configured to apply a control signal to the interconnect structure such that a specified subset of the set of memory devices performs a refresh operation.

US Patent:

6378018, Apr 23, 2002

Filed:

Oct 9, 1998

Appl. No.:

09/169506

Inventors:

Ely K. Tsern - Los Altos CA
Thomas J. Holman - Portland OR
Richard M. Barth - Palo Alto CA
Andrew V. Anderson - Portland OR
Paul G. Davis - San Jose CA
Craig E. Hampel - San Jose CA
Donald C. Stark - Los Altos CA
Abhijit M. Abhyankar - Sunnyvale CA

Assignee:

Intel Corporation - Santa Clara CA
Rambus, Inc. - Los Altos CA

International Classification:

G06F 1300

US Classification:

710129, 710128, 713323, 713320, 711105, 711 5

Abstract:

A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure.

US Patent:

6453393, Sep 17, 2002

Filed:

Sep 18, 2000

Appl. No.:

09/663918

Inventors:

Thomas J. Holman - Portland OR
Andrew V. Anderson - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711154, 711105

Abstract:

A memory system includes a primary memory interface, coupled to a primary device, adapted to receive memory requests from the primary device, and to transmit memory device independent requests based on the memory requests from the primary device. An external memory interface is coupled to at least one memory device via a memory interconnect. A memory independent interconnect, coupled to the primary memory interface and the external memory interface, is adapted to transport the memory device independent requests from the primary memory interface to the external memory interface.

US Patent:

6523098, Feb 18, 2003

Filed:

Dec 22, 1999

Appl. No.:

09/469676

Inventors:

Andrew V. Anderson - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711158, 711156, 711163

Abstract:

In one embodiment, a method and apparatus for servicing a request for an opportunistic operation to a memory subsystem includes an enabling signal that is generated to service the request for the opportunistic operation according to any combination of the following information: availability of resources of the memory subsystem, status of pending requests for a high priority operation, and status of the request for the opportunistic operation.

US Patent:

6529968, Mar 4, 2003

Filed:

Dec 21, 1999

Appl. No.:

09/469171

Inventors:

Andrew V. Anderson - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1314

US Classification:

710 22, 710 26, 710 55, 711141, 711145, 711146, 711150, 711152, 711168

Abstract:

In a computer system, an agent, a DMA controller and a memory controller are provided, each in communication with a bus. The DMA controller and the memory controller also can communicate with each other via a second communication path. The computer system may include a memory provided in communication with the memory controller having a coherent memory space and a non-coherent memory space. The DMA controller transfers a portion of data from the coherent memory space with a portion of data from the non-coherent memory space with a single transaction on the external bus.

US Patent:

6594730, Jul 15, 2003

Filed:

Aug 3, 1999

Appl. No.:

09/365851

Inventors:

Herbert H J Hum - Portland OR
Andrew V. Anderson - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

711137, 711118, 711154, 711204, 711213, 712207, 712237

Abstract:

An embodiment of the present invention provides a memory controller that includes a plurality of transaction queues and an arbiter, a prefetch cache in communication with the arbiter, and a prefetch queue in communication with the prefetch cache. The prefetch queue also may be provided in communication with each of the transaction queues for the purpose of determining whether the transaction queues are operating in a congested state.

US Patent:

6622087, Sep 16, 2003

Filed:

Dec 26, 2000

Appl. No.:

09/748813

Inventors:

Andrew V. Anderson - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01C 2100

US Classification:

701209, 701201, 701117

Abstract:

A route request is received from a user to travel from a start location to a destination location. A route guidance is provided for a route to the destination location based on a travel profile for the user in response to the route request. The travel profile comprises one or more of a history of driving behavior of the user and a driving preference specified by the user.

US Patent:

6651115, Nov 18, 2003

Filed:

Jan 6, 2003

Appl. No.:

10/336720

Inventors:

Andrew V. Anderson - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1314

US Classification:

710 22, 710 26, 710 55, 711141, 711145, 711146, 711150, 711152, 711168

Abstract:

In a computer system, an agent, a DMA controller and a memory controller are provided, each in communication with a bus. The DMA controller and the memory controller also can communicate with each other via a second communication path. The computer system may include a memory provided in communication with the memory controller having a coherent memory space and a non-coherent memory space. The DMA controller transfers a portion of data from the coherent memory space with a portion of data from the non-coherent memory space with a single transaction on the external bus.