Andrew B Chen

US Patent:

6870233, Mar 22, 2005

Filed:

Aug 14, 2003

Appl. No.:

10/642077

Inventors:

Bomy Chen - Cupertino CA, US
Kai Man Yue - Yuen Long N.T., HK
Andrew Chen - Bedminster NJ, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L029/76
H01L021/8236
G11C017/00

US Classification:

257390, 257391, 257408, 257344, 257345, 438276, 438278, 365104, 365182

Abstract:

A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart from one another are in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. The ROM cell has one of a plurality of N possible states, where N is greater than 2. The possible states of the ROM cell are determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

US Patent:

7642946, Jan 5, 2010

Filed:

Apr 7, 2008

Appl. No.:

12/098842

Inventors:

Marcel L. Lugthart - Aliso Viejo CA, US
Andrew R. Chen - Redondo Beach CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 1/34

US Classification:

341163, 341154, 341144, 341155

Abstract:

A system and method are provided allowing for successive approximation analog to digital conversion. A first differential voltage is sampled and held during a first cycle. The first differential voltage is converted to a differential current. A second differential voltage is generated based on the differential current flowing through parallel-coupled respective first and second variable resistances. First and second portions of the second differential voltage are compared to produce a comparison result therefrom. Successive approximation is used to generate a signal based on the comparison result, the signal being an output signal and being used to control resistances of respective ones of the first and second variable resistances during subsequent cycles.

US Patent:

7805366, Sep 28, 2010

Filed:

Mar 19, 2004

Appl. No.:

10/805414

Inventors:

Andrew Dali Chen - Santa Clara CA, US
Brian Andrew Phillips - San Francisco CA, US
Chad Meredith Hurley - Palo Alto CA, US
Dantley Davis - San Jose CA, US
Paul Arthur Martin - Menlo Park CA, US
Yu Pan - Mountain View CA, US

Assignee:

eBay Inc. - San Jose CA

International Classification:

G06Q 40/00

US Classification:

705 40, 705 39, 705 42

Abstract:

A payment system includes a transaction identification system to identify a plurality of purchase transactions, established utilizing one or more transaction systems that impose a plurality of corresponding payment obligations on a particular user. An interface generator generates an aggregation interface that presents the plurality of purchase transactions to the first user. The plurality of purchase transactions are presented in conjunction with a payment option to initiate an automatic payment process with respect to at least a subset of the purchase transactions. A payment engine initiates the automatic payment process with respect to the first subset of plurality of purchase transactions upon election by the first user of the payment option.

US Patent:

7944251, May 17, 2011

Filed:

Mar 9, 2009

Appl. No.:

12/381227

Inventors:

Andrew Chen - Redondo Beach CA, US
Joseph Aziz - Irvine CA, US
Derek Tam - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03B 1/00

US Classification:

327108, 327109, 327512

Abstract:

According to one exemplary embodiment, a transmitter module includes a line drive including a current digital-to-analog converter, where the line driver provides an analog output waveform. The current digital-to-analog converter receives a digitally filtered input waveform including at least two voltage steps. The at least two voltage steps of the digitally filtered input waveform cause a rise time of the analog output waveform to have a reduced dependency on process, voltage, and temperature variations in the line driver, while meeting stringent rise time requirements. The digitally filtered input waveform has an initial voltage level and a final voltage level, where the final voltage level is substantially equal to a sum of the at least two voltage steps of the digitally filtered input waveform.

US Patent:

7982491, Jul 19, 2011

Filed:

Apr 8, 2009

Appl. No.:

12/384793

Inventors:

Joseph Aziz - Irvine CA, US
Andrew Chen - Redondo Beach CA, US
Derek Tam - Irvine CA, US
Agnes Neves Woo - Encino CA, US
Marcel Lugthart - Aliso Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03K 17/16
H03K 19/003

US Classification:

326 30, 326 34, 326 86

Abstract:

According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.

US Patent:

8007187, Aug 30, 2011

Filed:

May 27, 2010

Appl. No.:

12/789384

Inventors:

Andrew Chen - Cupertino CA, US

International Classification:

G03B 15/00
G03B 19/12
H04N 5/225

US Classification:

396352, 396358, 348374

Abstract:

A lens-interchangeable single-lens reflex camera system according to the present invention employs a novel reflex apparatus comprising stationary “smart glass” elements. The “smart glass” elements switch between transparent and non-transparent states in response to applied electrical voltage, allowing for silent, solid-state control of the optical light path from an external scene image. The optical transmittances of the “smart glass” elements are electronically regulated to provide the operator with a representation of the scene image through the optical viewfinder during the inactive observation period, and to alternately allow the external light to reach the image-sensing device during a photographic exposure.

US Patent:

8183885, May 22, 2012

Filed:

Apr 8, 2009

Appl. No.:

12/384795

Inventors:

Joseph Aziz - Irvine CA, US
Andrew Chen - Redondo Beach CA, US
Derek Tam - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03K 19/094

US Classification:

326 86, 326 83, 327109, 341145

Abstract:

In one embodiment, a circuit for providing a tail current for a line driver includes an adjustable current source. The adjustable current source includes a number of current source cells coupled together in a parallel configuration, where the current source cells are configured to provide the tail current for the line driver in response to a digital control signal. The circuit can further include a digital core coupled to the adjustable current source, where the digital core provides the digital control signal. The digital control signal provides a number of bits, where each bit controls one of the current source cells. In one embodiment, a current source cell can comprise a number of current source sub-cells. The current source cells can be configured to provide the tail current for the line driver in response to the digital control signal when the line driver is operating in a class AB mode.

US Patent:

8243510, Aug 14, 2012

Filed:

Aug 30, 2006

Appl. No.:

11/514029

Inventors:

Andrew Chen - Redondo Beach CA, US
Bibhudatta Sahoo - San Diego CA, US
Ali Anvar - Aliso Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 11/34

US Classification:

36518501, 36518514, 257315

Abstract:

According to one exemplary embodiment, a memory cell in a semiconductor chip includes a non-volatile memory transistor, a control gate, and a floating gate. The control gate is capacitively coupled to the floating gate of the non-volatile memory transistor by a metal capacitor. The metal capacitor can be formed in one or more metal levels and in one embodiment is in a shape of a comb with multiple fingers. In one embodiment, the non-volatile memory transistor is an NMOS non-volatile memory transistor.