Andrew Richard Fox

US Patent:

6801052, Oct 5, 2004

Filed:

Oct 11, 2002

Appl. No.:

10/269830

Inventors:

Daniel J. Pugh - San Jose CA
Andrew W. Fox - Pacific Grove CA
Dale Wong - San Francisco CA

Assignee:

Leopard Logic, Inc. - Cupertino CA

International Classification:

H01L 2500

US Classification:

326 39, 326 38, 326 41, 326 46

Abstract:

A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.

US Patent:

7009421, Mar 7, 2006

Filed:

Sep 27, 2004

Appl. No.:

10/951309

Inventors:

Daniel J. Pugh - San Jose CA, US
Andrew W. Fox - Pacific Grove CA, US
Dale Wong - San Francisco CA, US

Assignee:

Agate Logic, Inc. - Cupertino CA

International Classification:

H03K 19/173
G06F 17/50

US Classification:

326 38, 326 39, 326 40, 716 7, 716 17

Abstract:

A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.

US Patent:

20160321039, Nov 3, 2016

Filed:

Apr 29, 2016

Appl. No.:

15/142595

Inventors:

- Campbell CA, US
Andrew William Fox - Santa Cruz CA, US
Tigran Sargsyan - Yerevan, AM

International Classification:

G06F 9/44
G06F 3/06

Abstract:

Technology mapping onto code fragments and related concepts are disclosed. Program descriptions are obtained in a high-level language. One or more intrinsic libraries containing modules are obtained. The modules correspond to sections of code intended for execution on the special purpose hardware. The high-level program description is analyzed to determine locations of one or more cuts within the program. The cuts represent portions of the high-level code that are eligible for replacement by one or more modules from intrinsic libraries. A matching process is used to find modules that are suitable replacements for the high level code. Once the replacements are made, additional verification and/or validation are performed by compiler checking and/or execution tests.