Andrew P Freemyer from Austin, TX, age 49

Andrew Freemyer Phones & Addresses

Austin, TX
Oronoco, MN
Rochester, MN
Eden Prairie, MN
Helotes, TX

Work

Company:

Nvidia
Jan 2013
Address:

Austin, Texas Area
Position:

Senior hardware engineer

Education

Degree:

MS
School / High School:

University of Minnesota-Twin Cities
1999 to 2003
Specialities:

Electrical Engineering

Skills

Static Timing Analysis • Timing Closure • Physical Design • Soc • Tcl • Verilog • Vhdl • Logic Synthesis • Floorplanning • Synopsys Primetime • Dft • Physical Synthesis

Industries

Computer Hardware

Resumes

Senior Hardware Engineer

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Location:

300 Pettigru St, Greenville, SC 29601

Industry:

Computer Hardware

Work:

NVIDIA - Austin, Texas Area since Jan 2013
Senior Hardware Engineer
AMD Aug 2011 - Jan 2013
Member of Technical Staff
IBM - Rochester, MN Aug 1998 - Aug 2011
Senior Engineer

Education:

University of Minnesota-Twin Cities 1999 - 2003
MS, Electrical Engineering North Dakota State University 1994 - 1998
BS, Electrical Engineering

Skills:

Static Timing Analysis
Timing Closure
Physical Design
Soc
Tcl
Verilog
Vhdl
Logic Synthesis
Floorplanning
Synopsys Primetime
Dft
Physical Synthesis

Us Patents

Reciprocal Estimate Computation Methods And Apparatus
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US Patent:

20070112902, May 17, 2007
Filed:

Nov 17, 2005
Appl. No.:

11/282032
Inventors:

Sherman Dance - Rochester MN, US
Andrew Freemyer - Rochester MN, US
Matthew Tubbs - Rochester MN, US
Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY
International Classification:

G06F 7/552
US Classification:

708500000
Abstract:

In a first aspect, a first method of reciprocal estimate computation using floating point pipeline logic is provided. The first method includes the steps of (1) receiving an input value having an exponent and a mantissa when represented as a floating point number on which a reciprocal estimate computation is to be performed; (2) determining whether the exponent is one of a plurality of predetermined numbers; and (3) if the exponent is one of the plurality of predetermined numbers, adjusting at least one of a plurality of modified mantissa bits (e.g., mantissa bits internal to leading zero anticipator (LZA) logic) and the exponent so as to prevent an underflow result of the reciprocal estimate computation. Numerous other aspects are provided.

Andrew P Freemyer