Andrew G Marshall

US Patent:

6373094, Apr 16, 2002

Filed:

Jul 18, 2001

Appl. No.:

09/908024

Inventors:

Andrew Marshall - Dallas TX
Joseph A. Devore - Dallas TX
Ross E. Teggatz - McKinney TX
Wayne T. Chen - Plano TX
Ricky D. Jordanger - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29788

US Classification:

257315, 257314, 36518501

Abstract:

An EEPROM cell ( ) formed on a substrate ( ) using conventional process steps is provided. The cell ( ) includes first ( ) and second ( ) conductive regions in the substrate ( ) below the substrates outer surface ( ), and the first ( ) and second ( ) conductive regions are laterally displaced from one another by a predetermined distance ( ). The cell ( ) also includes an insulating layer ( ) outwardly from the outer surface ( ) of the substrate ( ) positioned so that its edges are substantially in alignment between the first ( ) and second ( ) conductive regions. The cell ( ) further includes a floating gate layer ( ) outwardly from the insulating layer ( ) and in substantially the same shape as the insulating layer ( ). The cell ( ) also includes a diffusion region ( or ) that extends laterally from at least one of the first ( ) and second ( ) conductive regions so as to overlap with the insulating layer ( ). The diffusion region ( or ) provides a source of charge for placement on the floating gate layer ( ) when programming the EEPROM cell ( ).

US Patent:

6628540, Sep 30, 2003

Filed:

Dec 31, 2001

Appl. No.:

10/036324

Inventors:

Andrew Marshall - Dallas TX
Theodore W. Houston - Richardson TX
Sreedhar Natarajan - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1100

US Classification:

365154, 365156, 36523006

Abstract:

Quiescent current drawn by an array of four-transistor loadless static random access memory (SRAM) cells is minimized by using a negative feedback loop to set a reference voltage, for the wordline driver, to a level which reduces the subthreshold current through the pass transistors to a level which is just barely sufficient to reliably retain data.

US Patent:

6642601, Nov 4, 2003

Filed:

Oct 25, 2001

Appl. No.:

10/001591

Inventors:

Andrew Marshall - Dallas TX
Douglas A. Prinslow - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2900

US Classification:

257529, 257625, 257755, 257773

Abstract:

A fuse ( ) with a low fusing current includes a first contact element ( ) and a second contact element ( ). A fusing element ( ) is coupled between the first and second contact elements ( ). At least a majority of the fusing element ( ) comprises silicided material.

US Patent:

6717530, Apr 6, 2004

Filed:

Aug 14, 2000

Appl. No.:

09/638839

Inventors:

Thomas A. Schmidt - Dallas TX
Andrew Marshall - Dallas TX
Jingwei Xu - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G08B 2926

US Classification:

34087017, 34087016, 702130, 702132

Abstract:

A temperature sensing system ( ) that providing at least one detect signal related to temperature in an integrated circuit is presented. This system uses one thermal sensing circuit ( ) to detect two or more temperature thresholds (t , t ) and differentiates the temperature thresholds using time multiplexed logic control. The system ( ) capable of detecting more than two temperatures includes the thermal sensing circuit ( ) and a decode circuit ( ) with at least one detect latch ( ). Optionally, the system may include a hysteresis circuit ( ). The thermal sensing circuit ( ), connected to the integrated circuit, generates a detect signal (D ) in response to the a temperature selection signal (T ). This flexible on-board temperature monitoring solution reduces the cost of thermal feedback sensing by reducing die area and improves the correlation of detected temperatures. In addition, this solution reduces the possibility of mismatch and tracking errors between two or more sense elements.

US Patent:

6773972, Aug 10, 2004

Filed:

Dec 13, 2001

Appl. No.:

10/023113

Inventors:

Andrew Marshall - Dallas TX
Youngmin Kim - Allen TX
David B Scott - Plano TX
Douglas E. Mercer - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21338

US Classification:

438176, 438181, 438184, 438217, 438231, 438276, 257204, 257288, 257341, 257371

Abstract:

A method of forming a semiconductor circuit ( ). The method forms a first transistor (NT ) using various steps, such as by forming a first source/drain region ( ) as a first doped region in a fixed relationship to a semiconductor substrate ( ) and forming a second source/drain region ( ) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate ( ) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST ) using various steps, such as by forming a third source/drain region ( ) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region ( ) as a fourth doped region in a fixed relationship to the semiconductor substrate. The fourth doped region and the third doped region are of the same conductivity type as the first and second doped regions. Additionally, the second transistor is formed by forming a second gate ( ) in a fixed relationship to the third source/drain region and the fourth drain region.

US Patent:

6819123, Nov 16, 2004

Filed:

Aug 8, 2002

Appl. No.:

10/215223

Inventors:

Andrew Marshall - Dallas TX
Victor C. Sutcliffe - Frisco TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 2708

US Classification:

324711, 324 7654, 324677, 331 57

Abstract:

The apparatus for detecting the effects of interconnect resistance and capacitance (RC) in a logic circuit includes a first ring oscillator with the interconnect RC parasitics in a logic circuit and a minimum reference ring oscillator without the interconnect RC parasitic in a logic circuit multiplexed to have common stages to obtain delay with and without the parasitics of the interconnect RC. The frequency difference between the first ring oscillator frequency and the minimum reference ring oscillator frequency is determined to detect the effects of the interconnect RC in the logic circuit.

US Patent:

6844751, Jan 18, 2005

Filed:

Sep 26, 2001

Appl. No.:

09/965452

Inventors:

Andrew Marshall - Dallas TX, US
George E. Harris - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 3126

US Classification:

324765, 324 731, 3241581

Abstract:

A test selector that multiplexes different test structures () to an adjacent probe pad () in dependence on the probe voltage. In addition, a scribeline test circuit is disclosed that includes a test selector circuit located in a single scribeline portion between two adjacent die locations. Multiple test structures and at least one probe pad also are located in the single scribeline portion. The test selector circuit makes an electrical connection from the probe pad to a selected one of the test structures depending upon a voltage applied at the probe pad.

US Patent:

6947310, Sep 20, 2005

Filed:

May 13, 2004

Appl. No.:

10/844834

Inventors:

Andrew Marshall - Dallas TX, US
Sumanth Katte Gururajarao - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C011/22

US Classification:

365145, 365154

Abstract:

Ferroelectric latch type memory devices () are provided, comprising an input circuit () with first and second internal nodes (N, N) coupled with first and second ferroelectric capacitors (C, C), a control circuit (), a restore circuit (), and an output circuit (). The input circuit () operates in a first mode to provide the input data state as first and second voltages on the first and second internal nodes (N, N), respectively. In a second mode, the input circuit () allows the internal nodes (N, N) to float, the restore circuit () operates to restore the data state from the ferroelectric capacitors (C, C) to the internal nodes (N, N), and the output circuit () provides a restored data state as an output (OUT).