Ann T Wu

US Patent:

7095247, Aug 22, 2006

Filed:

Mar 25, 2004

Appl. No.:

10/809658

Inventors:

Howard Tang - Cupertino CA, US
Satwant Singh - Fremont CA, US
Ann Wu - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 7/38

US Classification:

326 38, 326 39, 36518901, 36523001, 36523002

Abstract:

The configuration architecture for a programmable device, such as an FPGA, includes one or more memory devices connected directly to the FPGA such that the FPGA can be configured with configuration data stored in the memory devices without transmitting the configuration data via a controller connected between any of the memory devices and the FPGA. In one embodiment, the FPGA has an Serial Peripheral Interface (SPI) that is connected to the SPI interface of each of one or more SPI serial flash PROMs operating as boot PROMs. When there are two or more boot PROMs, each PROM stores a portion of the FPGA's configuration data and the FPGA interleaves the data from multiple boot PROMs to generate a serial configuration data bitstream. The present invention enables boot PROMs having different sizes and/or storing different amounts of configuration data to be simultaneously connected to an FPGA to support efficient configuration architectures.

US Patent:

7257750, Aug 14, 2007

Filed:

Jan 13, 2005

Appl. No.:

11/036630

Inventors:

Satwant Singh - Fremont CA, US
Chi Nguyen - San Jose CA, US
Ann Wu - San Jose CA, US
Ting Yew - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G01R 31/28
G06F 11/00

US Classification:

714732, 714736

Abstract:

In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.

US Patent:

7401280, Jul 15, 2008

Filed:

May 18, 2007

Appl. No.:

11/750790

Inventors:

Satwant Singh - Fremont CA, US
Chi Nguyen - San Jose CA, US
Ann Wu - San Jose CA, US
Ting Yew - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G01R 31/28
G06F 11/00

US Classification:

714732, 714736

Abstract:

In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.

US Patent:

7589648, Sep 15, 2009

Filed:

Feb 10, 2005

Appl. No.:

11/054855

Inventors:

Benny Ma - Saratoga CA, US
Ann Wu - San Jose CA, US
Thomas Tsui - Cupertino CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03M 7/00

US Classification:

341 87, 341 50, 341 65, 341 67, 326 37, 326 38, 707101

Abstract:

In one embodiment, a data decompression circuit for a data stream having a repeated data word is provided. The data stream is compressed into a series of data frames such that the repeated data word is removed from the series of data frames and such that each data frame corresponds to a header. The circuit includes a decompression engine configured to decompress each data frame into a corresponding decompressed data frame, the decompression engine being further configured to decode each header to identify whether word locations in the corresponding decompressed data frame should be filled with the repeated data word.

US Patent:

7596744, Sep 29, 2009

Filed:

Feb 24, 2006

Appl. No.:

11/361584

Inventors:

Ann Wu - San Jose CA, US
Tou Nou Thao - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F 7/02
G01R 31/28

US Classification:

714819

Abstract:

In one embodiment, a programmable logic device for recovery from soft error upsets (SEUs) includes: a configuration memory operable to store configuration data; a configuration engine operable to configure the configuration memory; an error detection circuit operable to determine if the stored configuration data in the configuration memory has an error; and a configuration reset circuit operable to trigger the configuration engine to reconfigure the configuration memory if the error detection circuit detects the error.

US Patent:

7631223, Dec 8, 2009

Filed:

Jun 6, 2006

Appl. No.:

11/447591

Inventors:

Roger Spinti - San Jose CA, US
Howard Tang - San Jose CA, US
Ann Wu - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F 11/00

US Classification:

714 36, 714 27

Abstract:

Various techniques are disclosed herein to provide an improved approach to the loading of configuration data into configuration memory of programmable logic devices. For example, in accordance with one embodiment of the present invention a method of configuring a programmable logic device includes reading a first bitstream from a first memory block of an external memory device. The first bitstream is checked for errors and a second bitstream is read from a second memory block of the external memory device if an error is detected. Configuration memory of the programmable logic device is programmed with configuration data provided in one of the first bitstream and the second bitstream.

US Patent:

7725803, May 25, 2010

Filed:

Nov 8, 2006

Appl. No.:

11/557808

Inventors:

Howard Tang - San Jose CA, US
Roger Spinti - Milpitas CA, US
Ann Wu - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03M 13/00
G01R 31/28

US Classification:

714758, 714725

Abstract:

In accordance with an embodiment of the present invention, a programmable logic device includes configuration memory to store configuration data to configure the programmable logic device, and a non-volatile memory to store configuration data for transfer to the configuration memory to configure the programmable logic device. The non-volatile memory also stores a first code value based on the configuration data stored in the non-volatile memory. A code block calculates a second code value based on the configuration data transferred to the configuration memory. A comparator compares the first code value to the second code value to verify that the configuration data was not corrupted during the transfer from the non-volatile memory to the configuration memory.

US Patent:

7902865, Mar 8, 2011

Filed:

Nov 15, 2007

Appl. No.:

11/941031

Inventors:

Chan-Chi Jason Cheng - Fremont CA, US
Ann Wu - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H01L 25/00
H03M 5/00
G06F 17/50

US Classification:

326 41, 341 55, 716117

Abstract:

Various techniques are provided to compress and decompress configuration data for use with programmable logic devices (PLDs). In one example, a method includes embedding a first data frame comprising a data set from an uncompressed bitstream into a compressed bitstream. The method also includes embedding a first instruction to instruct a PLD to load the first data frame into a data shift register, embedding a second instruction to instruct the PLD to load a first address associated with the first data frame into an address shift register, and embedding a third instruction to instruct the PLD to load the first data frame from the data shift register into a first row of a configuration memory corresponding to the first address. The method further includes identifying a second data frame comprising the data set in the uncompressed bitstream, and embedding fourth and fifth instructions in place of the second data frame.