Anthony D Polson

US Patent:

7280939, Oct 9, 2007

Filed:

Apr 29, 2004

Appl. No.:

10/709362

Inventors:

David J. Hathaway - Underhill VT, US
Jerry D. Hayes - Milton VT, US
Anthony D. Polson - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/30
G06F 9/45

US Classification:

702182, 716 6

Abstract:

Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of interest, and the size of the bounding region may be used to calculate a timing slack variation factor. The size of the bounding region may be adjusted to account for variability in timing delays. In other embodiments, centroids may be calculated using either the location or the delay-weighted location of elements or cells within the path or cone and the centroids used to calculate timing slack variation factor. The timing slack variation factors are used to calculate a new timing slack for the path or logic cone of the circuit.

US Patent:

7290191, Oct 30, 2007

Filed:

Aug 20, 2004

Appl. No.:

10/711075

Inventors:

Gary D. Grise - Colchester VT, US
Steven F. Oakland - Colchester VT, US
Anthony D. Polson - Jericho VT, US
Philip S. Stevens - Williston VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714726, 714731

Abstract:

A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.

US Patent:

7302673, Nov 27, 2007

Filed:

Sep 15, 2005

Appl. No.:

11/162586

Inventors:

Peter Anton Habitz - Hinesburg VT, US
David James Hathaway - Underhill VT, US
Jerry D. Hayes - Milton VT, US
Anthony D. Polson - Jericho VT, US
Tad Jeffrey Wilder - South Hero VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 21, 716 19

Abstract:

A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.

US Patent:

7401307, Jul 15, 2008

Filed:

Nov 3, 2004

Appl. No.:

10/904309

Inventors:

Eric A. Foreman - Fairfax VT, US
Peter A. Habitz - Hinesburg VT, US
David J. Hathaway - Underhill VT, US
Jerry D. Hayes - Milton VT, US
Jeffrey H. Oppold - Richmond VT, US
Anthony D. Polson - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6, 716 2, 716 4

Abstract:

A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

US Patent:

7418689, Aug 26, 2008

Filed:

Apr 27, 2005

Appl. No.:

10/908102

Inventors:

Peter A. Habitz - Hinesburg VT, US
David J. Hathaway - Underhill VT, US
Jerry D. Hayes - Milton VT, US
Anthony D. Polson - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 14

Abstract:

A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

US Patent:

7444608, Oct 28, 2008

Filed:

May 15, 2006

Appl. No.:

11/383353

Inventors:

Eric A Foreman - Fairfax VT, US
Peter A Habitz - Hinesburg VT, US
David J Hathaway - Underhill VT, US
Jerry D Hayes - Mllton VT, US
Anthony D Polson - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6, 703 16

Abstract:

Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.

US Patent:

7487487, Feb 3, 2009

Filed:

Apr 1, 2008

Appl. No.:

12/060488

Inventors:

Anthony D. Polson - Jericho VT, US
David Lackey - Jericho VT, US
Theodoros E. Anemikos - Milton VT, US
Laura Chadwick - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6, 716 4

Abstract:

A design structure for monitoring of the performance of semiconductor circuits, such as circuit delay, across a chip. The design structure may include a clock source and a plurality of process monitors. The design structure may be used to construct a “schmoo plot” by varying a frequency of the clock source to determine the delay of process monitors at various locations across the chip.

US Patent:

7489204, Feb 10, 2009

Filed:

Jun 30, 2005

Appl. No.:

11/160603

Inventors:

Peter A. Habitz - Hinesburg VT, US
Anthony D. Polson - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 23/00
H03B 5/24
H03K 3/03

US Classification:

331 44, 331 57

Abstract:

Disclosed are a method and a structure for testing location-specific wire delay at a chip-level independent of silicon delay. The invention incorporates the use of a tester embedded in a metal layer of a chip. The tester comprises a ring oscillator that is selectively connected to either a first wire or a second wire by a multiplexer. A monitor measures ring frequencies of the ring oscillator when connected to either the first or second wire. A processor determines the wire delay based upon differences in the ring frequencies. Additional testers or multiple stages of a single tester may be embedded into either the same metal layer at a different location or into a different metal layer to allow for intra-metal layer or inter-metal layer comparisons of wire delay. Since metal capacitance and silicon load remains constant for both the first and second wires and the transient voltage change along the wire is hold small, metal delay is separable from delay due to silicon device performance. Pass/Fail criteria based upon a maximum allowable resistance-capacitance delay for a metal layer or based upon a comparison of resistance-capacitance delays across the same metal layer or between metal layers can be used to reject a chip.