Antonio M Marques

US Patent:

7068074, Jun 27, 2006

Filed:

Jun 30, 2004

Appl. No.:

10/881192

Inventors:

Dipankar Bhattacharya - Macungie PA, US
Makeshwar Kothandaraman - Whitehall PA, US
John C. Kriz - Palmerton PA, US
Antonio M. Marques - Summit NJ, US
Bernard L. Morris - Emmaus PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03K 19/0175
H03K 19/094

US Classification:

326 63, 326 68, 326 81, 326 83, 326 84, 326 85, 326 86, 326 87

Abstract:

A voltage level translator circuit for translating an input signal referenced to a first voltage level to an output signal referenced to a second voltage level includes an input stage for receiving the input signal. The input stage includes at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logical state of the input signal. The latch circuit includes at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp is operatively connected between the input stage and the latch circuit, the voltage clamp being configured to limit a voltage across the input stage based, at least in part, on a control signal presented thereto. The voltage level translator circuit includes a reference generator circuit for generating the control signal, a steady state value of the control signal being substantially equal to the first voltage level. The reference generator circuit is configured to adjust a voltage level of the control signal in response to the input signal.

US Patent:

7196561, Mar 27, 2007

Filed:

Aug 25, 2004

Appl. No.:

10/925613

Inventors:

Dipankar Bhattacharya - Macungie PA, US
John C. Kriz - Palmerton PA, US
Duane J. Loeper - Spring City PA, US
Antonio M. Marques - Summit NJ, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03L 7/00

US Classification:

327143, 327198

Abstract:

A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage. The voltage level detector is configured such that the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage.

US Patent:

7551020, Jun 23, 2009

Filed:

May 31, 2007

Appl. No.:

11/755955

Inventors:

Dipankar Bhattacharya - Macungie PA, US
Makeshwar Kothandaraman - Whitehall PA, US
John C. Kriz - Palmerton PA, US
Antonio M. Marques - Newark NJ, US
Bernard L. Morris - Emmaus PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G05F 1/10
G05F 3/02

US Classification:

327538, 327540, 327541, 327543

Abstract:

A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.

US Patent:

8373441, Feb 12, 2013

Filed:

Sep 20, 2011

Appl. No.:

13/236914

Inventors:

John A. Milinichik - Allentown PA, US
Peter J. Nicholas - Philadelphia PA, US
Carol A. Huber - Macungie PA, US
Antonio M. Marques - Newark NJ, US
Daniel J. Delpero - Allentown PA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 25/00
H03K 19/00

US Classification:

326101, 326 41, 326 47

Abstract:

Described embodiments provide for a semiconductor device comprising a core and one or more input/output (I/O) buffers surrounding the core. The I/O buffers are adapted to transfer signals associated with core circuitry of the core. The I/O buffers comprise I/O cells having a first orientation and I/O cells having a second orientation. Each I/O cell has a corresponding translator having low voltage transistors in a corresponding footprint. The low voltage transistors in the first orientation I/O cells have the first orientation, and the low voltage transistors in the second orientation I/O cells have the first orientation. The footprints of the first orientation I/O cells and the second orientation I/O cells are compatible with one another.