Aric W Griggs

US Patent:

7649836, Jan 19, 2010

Filed:

Sep 2, 2004

Appl. No.:

10/933688

Inventors:

Aric Griggs - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 12/26

US Classification:

370223, 713320

Abstract:

A link state machine for the Advanced Switching (AS) Architecture includes added transition sub-states. Transition events typically handled in AS link states are handled in the transition sub-states. Separating the transition events and flow from the link states into smaller transition sub-states may make the AS link machine easier to manage and facilitate debugging efforts.

US Patent:

8589613, Nov 19, 2013

Filed:

Jun 2, 2010

Appl. No.:

12/792490

Inventors:

Aric W. Griggs - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/36
G06F 15/163

US Classification:

710311, 710306

Abstract:

A method and system to improve the operations of an integrated non-transparent bridge device (NTB) that is coupled to another NTB device or Root Port device. The integrated NTB device has logic to maintain ordering of interrupts to be sent to the remote Root Port or NTB device. The integrated NTB device allocates a contiguous portion of the memory for both the primary Base Address Register 0 associated with the integrated NTB device and the secondary BAR0 associated with the remote NTB device. The integrated NTB device has logic to report the size of the primary BAR0 as the combined size of the primary BAR0 and the size of the secondary BAR0. The integrated NTB device facilitates the dynamic modification of a mapping of each bit of a doorbell register with a respective one of a plurality of interrupt vectors based on a mapping register.

US Patent:

20060050632, Mar 9, 2006

Filed:

Sep 3, 2004

Appl. No.:

10/934085

Inventors:

Aric Griggs - Chandler AZ, US

International Classification:

H04L 12/26

US Classification:

370229000

Abstract:

Devices in an Advanced Switching (AS) fabric may include state machines for controlling the generation and transmission of flow control (FC) update data link layer packets (DLLPs) between link partners. A link partner may use the state machine to generate flow control update DLLPs for all available virtual channels (VCs) and transmit the FC update DLLPs contiguously to prevent any given VC from failing to perform an FC update refresh within an FC update timeout period due to injection of large packets (e.g., AS transaction layer packets (TLPs)) between the FC Update DLLPs.

US Patent:

20060050716, Mar 9, 2006

Filed:

Sep 3, 2004

Appl. No.:

10/934644

Inventors:

Aric Griggs - Chandler AZ, US

International Classification:

H04L 12/56
H04L 12/28

US Classification:

370397000

Abstract:

An Advanced Switching (AS) device may include a generic state machine to handle flow control (FC) credit initialization and updates for all three types of virtual channels (VCs), i.e., bypass VCs (BVCs), ordered VCs (OVCs), and multicast VCs (MVCs), while handling each type of VC according to its unique requirements. The state machine may transition between states in response to signals from VC logic and disable signals a packet arbiter. The generic state machine may be instantiated for all VCs supported by the AS device.