Arnaldo R Cruz

US Patent:

7206244, Apr 17, 2007

Filed:

Dec 1, 2004

Appl. No.:

11/000560

Inventors:

Arnaldo R. Cruz - Austin TX, US
Qadeer A. Qureshi - Dripping Springs TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 7/00
G11C 5/06
G11C 7/04

US Classification:

365222, 365 63, 365211

Abstract:

A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e. g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.

US Patent:

7295484, Nov 13, 2007

Filed:

Mar 13, 2007

Appl. No.:

11/685419

Inventors:

Arnaldo R. Cruz - Austin TX, US
Qadeer A. Qureshi - Dripping Springs TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 7/00
G11C 7/04
G11C 5/06

US Classification:

365222, 365211, 365 63

Abstract:

A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e. g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.

US Patent:

7415558, Aug 19, 2008

Filed:

Dec 14, 2006

Appl. No.:

11/610956

Inventors:

Arnaldo R. Cruz - Austin TX, US
John J. Vaglica - Austin TX, US
William C. Moyer - Dripping Springs TX, US
Tuongvu V. Nguyen - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 13/24
G06F 13/00

US Classification:

710260, 710 38, 710104, 710266

Abstract:

New approaches for providing communication between multiple masters () and one or more shared resources () are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry () may be used to provide steering for additional signals such as interrupts. Other shared resources () may use more centralized circuitry () to perform a steering function for additional signals.

US Patent:

7623894, Nov 24, 2009

Filed:

Oct 9, 2003

Appl. No.:

10/682746

Inventors:

John J. Vaglica - Austin TX, US
Jose G. Corleto-Mena - Austin TX, US
Arnaldo R. Cruz - Austin TX, US
Jianping Tao - Cedar Park TX, US
Mieu V. Vu - Austin TX, US
Mark E. Elledge - Austin TX, US
Charbel Khawand - Miami FL, US
Arthur M. Goldberg - Parkland FL, US
David J. Hayes - Lake Worth FL, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H04M 1/00
H04B 1/38

US Classification:

455557, 455 84, 455418, 455419, 4555561, 370347

Abstract:

A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer processor operations, layer processor operations, and layer processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

US Patent:

8131316, Mar 6, 2012

Filed:

Oct 26, 2009

Appl. No.:

12/606044

Inventors:

John J. Vaglica - Austin TX, US
Jose G. Corleto-Mena - Austin TX, US
Arnaldo R. Cruz - Austin TX, US
Jianping Tao - Cedar Park TX, US
Mieu V. Vu - Austin TX, US
Mark E. Elledge - Austin TX, US
Charbel Khawand - Miami FL, US
Arthur M. Goldberg - Parkland FL, US
David J. Hayes - Lake Worth FL, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H04M 1/00
H04B 1/38

US Classification:

455557, 455 84, 455418, 455419, 4555561, 370347

Abstract:

A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

US Patent:

20050080961, Apr 14, 2005

Filed:

Oct 9, 2003

Appl. No.:

10/682571

Inventors:

Ryan Bedwell - Kyle TX, US
Arnaldo Cruz - Austin TX, US
John Vaglica - Austin TX, US
William Moyer - Dripping Springs TX, US

International Classification:

G06F013/36

US Classification:

710113000

Abstract:

New approaches for providing communication between multiple masters () and one or more shared resources () are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry () may be used to provide steering for additional signals such as interrupts. Other shared resources () may use more centralized circuitry () to perform a steering function for additional signals.

US Patent:

20050080966, Apr 14, 2005

Filed:

Oct 9, 2003

Appl. No.:

10/682558

Inventors:

Arnaldo Cruz - Austin TX, US
John Vaglica - Austin TX, US
William Moyer - Dripping Springs TX, US
Tuongvu Nguyen - Austin TX, US

International Classification:

G06F013/14

US Classification:

710240000

Abstract:

New approaches for providing communication between multiple masters () and one or more shared resources () are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry () may be used to provide steering for additional signals such as interrupts. Other shared resources () may use more centralized circuitry () to perform a steering function for additional signals.

US Patent:

20050102444, May 12, 2005

Filed:

Nov 7, 2003

Appl. No.:

10/703924

Inventors:

Arnaldo Cruz - Austin TX, US

International Classification:

G06F013/28

US Classification:

710022000, 711154000

Abstract:

One embodiment relates to a memory controller using an independent memory controller bus in order to transfer data between two or more memories. One embodiment of a data processing system includes a system bus, a system bus master coupled to the system bus, a first memory controller for controlling a first memory, a second memory controller for controlling a second memory, and a memory controller bus operating independent of the system bus to transfer data between the first memory controller and the second memory controller. The memory controller bus may include a data bus and read, write, and acknowledge signals. In one embodiment, the first memory is a block accessible memory such as a NAND Flash memory and the second memory is a random access memory (RAM) such as an SDRAM. The second memory may include arbitration logic for arbitrating between the system bus master and the first memory controller.