A digitally adjustable time delay circuit which is able to precisely and selectively provide fine delay steps increments, which increments can be one nth of the delay time of one CMOS inverter, including means to adjust the total range of the delay and size of each delay step.
Method And Apparatus For Transmitting And Receiving Both 8B/10B Code And 10B/12B Code In A Switchable 8B/10B Transmitter And Receiver
Marc C. Gleichert - San Jose CA Arthur Hsu - San Jose CA
International Classification:
H03M 700
US Classification:
341 95
Abstract:
A method and apparatus for using a modified 8B/10B system for transmitting 10 bit wide data packets in 12 bit code in which 5B/6B encoder/decoders separate the 10 bit wide data into two 5 bit nibbles. Unique special codes are provided which are not capable of aliasing with other 12 bit code words to provide reliable byte boundaries.
8B/10B Encoder Providing One Of Pair Of Noncomplementary, Opposite Disparity Codes Responsive To Running Disparity And Selected Commands
An 8B/10B encoder which provides an output of one of a pair of opposite disparity non-complementary 8B/10B command code outputs responsive to RD and selected command inputs.
Greenliant Systems
General Manager of Data Center Business Unit
Apacewave 2008 - 2012
Vice President of Engineering
Cortina Systems Mar 2007 - Aug 2008
Senior Director of Quality and Operations Engineering
Immenstar Aug 2004 - Feb 2007
Chief Executive Officer and Co-Founder
Chiplinks Jul 2002 - Jul 2004
Executive Vice President
Education:
National Chiao Tung University
Bachelors, Bachelor of Science
Arizona State University
Master of Science, Masters
Skills:
Soc Asic Ic Fpga Semiconductors Ethernet Engineering Management Embedded Systems Start Ups Verilog Lte Digital Signal Processors Electronics Mobile Devices Mixed Signal Project Management Wireless Wimax Wlan Pon Wifi Microprocessors Rf Firmware