Arthur Hsu

age ~67

from Mountain View, CA

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Also known as:

Chuanding A Hsu
Chuan Ding Hsu
Chuan Din Hsu
Chuan Ding Arthur Hsu
Chuan A Hsu
Chuan D Hsu
Chuanding D Hsu
Chuan-Ding Arthur Hsu
Arthur Hsu Chuanding
Ding Hsu

Phone and address:: 857 Avery Dr, Mountain View, CA 94043
(650)5278000

Connected to:

Arthur Hsu Phones & Addresses

857 Avery Dr, Mountain View, CA 94043 • (650)5278000
763 Almondwood Way, San Jose, CA 95120 • (408)2685616
Davis, CA
Flemington, NJ
Somerset, NJ

Work

Company:

Greenliant systems
2012
Position:

General manager of data center business unit

Education

Degree:

Bachelors, Bachelor of Science
School / High School:

National Chiao Tung University

Skills

Soc • Asic • Ic • Fpga • Semiconductors • Ethernet • Engineering Management • Embedded Systems • Start Ups • Verilog • Lte • Digital Signal Processors • Electronics • Mobile Devices • Mixed Signal • Project Management • Wireless • Wimax • Wlan • Pon • Wifi • Microprocessors • Rf • Firmware

Industries

Semiconductors

Us Patents

Digitally Adjustable Picosecond Delay Circuit
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US Patent:

55065341, Apr 9, 1996
Filed:

May 22, 1995
Appl. No.:

8/445891
Inventors:

Bin Guo - Fremont CA
Arthur Hsu - San Jose CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H03K 513
US Classification:

327276
Abstract:

A digitally adjustable time delay circuit which is able to precisely and selectively provide fine delay steps increments, which increments can be one nth of the delay time of one CMOS inverter, including means to adjust the total range of the delay and size of each delay step.

Method And Apparatus For Transmitting And Receiving Both 8B/10B Code And 10B/12B Code In A Switchable 8B/10B Transmitter And Receiver
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US Patent:

53879112, Feb 7, 1995
Filed:

Feb 21, 1992
Appl. No.:

7/839864
Inventors:

Marc C. Gleichert - San Jose CA
Arthur Hsu - San Jose CA
International Classification:

H03M 700
US Classification:

341 95
Abstract:

A method and apparatus for using a modified 8B/10B system for transmitting 10 bit wide data packets in 12 bit code in which 5B/6B encoder/decoders separate the 10 bit wide data into two 5 bit nibbles. Unique special codes are provided which are not capable of aliasing with other 12 bit code words to provide reliable byte boundaries.

8B/10B Encoder Providing One Of Pair Of Noncomplementary, Opposite Disparity Codes Responsive To Running Disparity And Selected Commands
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US Patent:

53049969, Apr 19, 1994
Filed:

Feb 21, 1992
Appl. No.:

7/839604
Inventors:

Arthur Hsu - San Jose CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H03M 700
US Classification:

341 95
Abstract:

An 8B/10B encoder which provides an output of one of a pair of opposite disparity non-complementary 8B/10B command code outputs responsive to RD and selected command inputs.

Resumes

General Manager Of Data Center Business Unit

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Location:

3970 Freedom Cir, Santa Clara, CA 95054

Industry:

Semiconductors

Work:

Greenliant Systems
General Manager of Data Center Business Unit
Apacewave 2008 - 2012
Vice President of Engineering
Cortina Systems Mar 2007 - Aug 2008
Senior Director of Quality and Operations Engineering
Immenstar Aug 2004 - Feb 2007
Chief Executive Officer and Co-Founder
Chiplinks Jul 2002 - Jul 2004
Executive Vice President

Education:

National Chiao Tung University
Bachelors, Bachelor of Science Arizona State University
Master of Science, Masters

Skills:

Soc
Asic
Ic
Fpga
Semiconductors
Ethernet
Engineering Management
Embedded Systems
Start Ups
Verilog
Lte
Digital Signal Processors
Electronics
Mobile Devices
Mixed Signal
Project Management
Wireless
Wimax
Wlan
Pon
Wifi
Microprocessors
Rf
Firmware