Arturo O Ruiz

US Patent:

20100155785, Jun 24, 2010

Filed:

Dec 22, 2008

Appl. No.:

12/342011

Inventors:

Huaqiang Wu - Burlingame CA, US
Hiro Kinoshita - San Jose CA, US
Ning Cheng - San Jose CA, US
Arturo Ruiz - San Jose CA, US
Jihwan Choi - San Mateo CA, US

Assignee:

SPANSION LLC - Sunnyvale CA

International Classification:

H01L 27/085
H01L 21/4763
H01L 29/78

US Classification:

257211, 438620, 257324, 257E21409, 257E29309, 257E2706

Abstract:

Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first bit lines and a pair of second bit lines. The first and second bit lines can be formed by an implant process using first and second spacers that have different lateral lengths from each other. The spacers can be used to offset the implants, thereby controlling the lateral lengths of the bit lines.