Ashraf W Lotfi

US Patent:

6351033, Feb 26, 2002

Filed:

Oct 6, 1999

Appl. No.:

09/413605

Inventors:

Ashraf W. Lotfi - Bridgewater NJ
John D. Weld - Ledgewood NJ

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H05K 502

US Classification:

257724, 257666, 257692, 257728, 257532, 257528, 257531, 257694, 257698, 257691, 257924, 363 17, 363 6 L, 363 98, 363141, 336232, 336200

Abstract:

The present invention provides a lead frame for use in packaging a circuit having a discrete component, and a method of manufacture thereof. In one embodiment, the lead frame includes a lead support structure and a plurality of severable leads that are coupled to the lead support structure. The plurality of severable leads extend inward from the lead support structure to predetermined locations corresponding to terminals of the discrete component.

US Patent:

6369408, Apr 9, 2002

Filed:

Oct 6, 1999

Appl. No.:

09/412847

Inventors:

Ashraf W. Lotfi - Bridgewater NJ
Jian Tan - Bridgewater NJ

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 2978

US Classification:

257 57, 257 59, 257347

Abstract:

A metal-oxide semiconductor field effect transistor (MOSFET), a method of manufacturing the MOSFET and a power supply incorporating at least one such MOSFET. In one embodiment, the MOSFET includes: (1) a substrate having an epitaxial layer underlying a gate oxide layer, a portion of the epitaxial layer being a gate region of the MOSFET, (2) an N-type drift region located in the epitaxial layer laterally proximate the gate region and (3) source and drain regions located in the epitaxial layer and laterally straddling the gate and drift regions.

US Patent:

6440750, Aug 27, 2002

Filed:

Feb 23, 2000

Appl. No.:

09/511343

Inventors:

Anatoly Feygenson - Hillsborough NJ
Dean P. Kossives - Glen Gardner NJ
Ashraf W. Lotfi - Bridgewater NJ
Lynn F. Schneemeyer - Westfield NJ
Michael L. Steigerwald - Martinsville NJ
R. Bruce Van Dover - Maplewood NJ

Assignee:

Agere Systems Guardian Corporation - Orlando FL

International Classification:

H01L 2100

US Classification:

438 3, 257798, 257421

Abstract:

A method of manufacturing an integrated circuit and an integrated circuit employing the same. In one embodiment, the method of manufacturing the integrated circuit includes (1) conformally mapping a micromagnetic device, including a ferromagnetic core, to determine appropriate dimensions therefor, (2) depositing an adhesive over an insulator coupled to a substrate of the integrated circuit and (3) forming the ferromagnetic core of the appropriate dimensions over the adhesive.

US Patent:

6495019, Dec 17, 2002

Filed:

Apr 19, 2000

Appl. No.:

09/552627

Inventors:

Robert William Filas - Bridgewater NJ
Trifon M Liakopoulos - Kings Park NY
Ashraf Wagih Lotfi - Bridgewater NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 2102

US Classification:

205119, 205125, 205126

Abstract:

The process is provided involving formation of multilayer components in which a photoresist-type material is used not only as a conventional patterning material, but also as an insulating and/or planarizing material between magnetic or electrically conductive layers. A variety of integrated CMOS/micromagnetic components are thereby capable of being formed, including components containing planar inductors and transformers. Additionally, a particular technique is used to etch gold-containing seed layers from a substrate surface without damaging an electroplated copper coil. Also provided is a magnetic material particularly useful in devices such as inductors and transformers. The material is an amorphous iron-cobalt-phosphorus alloy having a composition of Co P Fe , where x+y+z=100, x is 5 to 15, y is 13 to 20, and z is the remainder. The alloy typically exhibits a coercivity of 0. 1 to 0. 5 Oe, an electrical resistivity of 100 to 150 -cm, and a saturation magnetization of about 16 to about 19 kG, all of which represent improvements over Permalloy.

US Patent:

6541819, Apr 1, 2003

Filed:

May 24, 2001

Appl. No.:

09/865124

Inventors:

Ashraf W. Lotfi - Bridgewater NJ
Jian Tan - Bridgewater NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 2976

US Classification:

257335, 257266, 257337, 257341

Abstract:

The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a non-power enhanced metal oxide semiconductor (non-PEMOS) device having first source/drain regions located in a semiconductor substrate, wherein the first source/drain regions include a first dopant profile. The semiconductor device further includes a power enhanced metal oxide semiconductor (PEMOS) device located adjacent the non-PEMOS device and having second source/drain regions located in the semiconductor substrate, wherein the second source/drain regions include the first dopant profile.

US Patent:

6624498, Sep 23, 2003

Filed:

Dec 20, 2001

Appl. No.:

10/028594

Inventors:

Robert W. Filas - Bridgewater NJ
Trifon M. Liakopoulos - Long Beach NY
Ashraf Lotfi - Bridgewater NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 2900

US Classification:

257528, 257531, 257421, 336225

Abstract:

The process is provided involving formation of multilayer components in which a photoresist-type material is used not only as a conventional patterning material, but also as an insulating and/or planarizing material between magnetic or electrically conductive layers. A variety of integrated CMOS/micromagnetic components are thereby capable of being formed, including components containing planar inductors and transformers. Additionally, a particular technique is used to etch gold-containing seed layers from a substrate surface without damaging an electroplated copper coil. Also provided is a magnetic material particularly useful in devices such as inductors and transformers. The material is an amorphous iron-cobalt-phosphorus alloy having a composition of Co P Fe , where x+y+z=100, x is 5 to 15, y is 13 to 20, and z is the remainder. The alloy typically exhibits a coercivity of 0. 1 to 0. 5 Oe, an electrical resistivity of 100 to 150 -cm, and a saturation magnetization of about 16 to about 19 kG, all of which represent improvements over Permalloy.

US Patent:

6649422, Nov 18, 2003

Filed:

Jun 21, 2001

Appl. No.:

09/886780

Inventors:

Dean P. Kossives - Glen Gardner NJ
Ashraf W. Lotfi - Bridgewater NJ
Lynn F. Schneemeyer - Westfield NJ
Michael L. Steigerwald - Martinsville NJ
R. Bruce Van Dover - Maplewood NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 2100

US Classification:

438 3, 438800, 365145, 365157, 365158, 365171

Abstract:

An integrated circuit and method of manufacturing therefor. In one embodiment, the integrated circuit includes a substrate with an insulator and a capacitor formed over the substrate. The integrated circuit further includes an adhesive formed over the insulator. The integrated circuit still further includes a micromagnetic device. The micromagnetic device includes a ferromagnetic core formed over the adhesive. The adhesive forms a bond between the insulator and the ferromagnetic core to secure the ferromagnetic core to the substrate. The micromagnetic device also includes at least one winding, located proximate the ferromagnetic core, to impart a desired magnetic property to the ferromagnetic core. The micromagnetic device is electrically coupled to the capacitor.

US Patent:

6682962, Jan 27, 2004

Filed:

Aug 10, 2001

Appl. No.:

09/927194

Inventors:

Ashraf W. Lotfi - Bridgewater NJ
Jian Tan - Bridgewater NJ

Assignee:

Agere Systems, Inc. - Allentown PA

International Classification:

H01L 2100

US Classification:

438149, 438454

Abstract:

A metal-oxide semiconductor field effect transistor (MOSFET), a method of manufacturing the MOSFET and a power supply incorporating at least one such MOSFET. In one embodiment, the MOSFET includes: (1) a substrate having an epitaxial layer underlying a gate oxide layer, a portion of the epitaxial layer being a gate region of the MOSFET, (2) an N-type drift region located in the epitaxial layer laterally proximate the gate region and (3) source and drain regions located in the epitaxial layer and laterally straddling the gate and drift regions.