Atsushi Satoh
age ~85
from Dallas, TX
Atsushi Satoh Phones & Addresses
- Dallas, TX
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Atsushi Satoh
view sourceUs Patents
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Reduced Size Plate Layer Improves Misalignments For Cub Dram
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US Patent:6873001, Mar 29, 2005
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Filed:Jun 10, 1999
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Appl. No.:09/332360
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Inventors:Toshiyuki Nagata - Plano TX, US
Hiroyuki Yoshida - Plano TX, US
Masayuki Moroi - Richardson TX, US
Atsushi Satoh - Dallas TX, US -
Assignee:Texas Instruments Incorporated - Dallas TX
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International Classification:H01L027/108
H01L029/76
H01L029/94
H01L031/119 -
US Classification:257306, 257296
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Abstract:In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in connections between the bitline and the underlying transistors.
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Reduced Size Plate Layer Improves Misalignments In Cub Dram
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US Patent:20050030804, Feb 10, 2005
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Filed:Sep 7, 2004
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Appl. No.:10/936735
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Inventors:Toshiyuki Nagata - Plano TX, US
Hiroyuki Yoshida - Plano TX, US
Masayuki Moroi - Richardson TX, US
Atsushi Satoh - Dallas TX, US -
International Classification:H01B013/00
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US Classification:365202000
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Abstract:In a DRAM array using a capacitor-under-bitline (CUB) layout, the plate layer of the capacitor is significantly reduced in area to reduce misalignments in connections between the bitline and the underlying transistors.
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