Babak Nejati from 3316 Lower Ridge Rd, San Diego, CA 92130, age 48

Us Patents

Offset Nulling For Decreasing Offset Between Currents In A Differential Signaling System
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US Patent:

7825714, Nov 2, 2010
Filed:

Jun 12, 2008
Appl. No.:

12/137984
Inventors:

John B. Groe - Poway CA, US
Michael Naone Farias - San Diego CA, US
Babak Nejati - San Diego CA, US
Marc Facchini - San Diego CA, US
Thomas Hardin - Encinitas CA, US
Assignee:

Quintic Holdings - Santa Clara CA
International Classification:

H03L 5/00
US Classification:

327307, 327563, 330253
Abstract:

Systems and methods for nulling offsets in differential signaling systems are described. A first circuit may be configured to sense the difference between a first differential current and a second differential current and provide a sense signal to an adjustment circuit. The adjustment circuit may be configured to generate a correction signal based on the sense signal, where the correction signal is combined with the first differential current to reduce the offset between the first differential current and the second differential current. Alternately, the correction signal may be combined with the first and second differential currents to reduce the offset. The process may be repeated until the corrected first differential current and the second differential current are within a desired tolerance.

Digital Tunable Inter-Stage Matching Circuit
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US Patent:

8072272, Dec 6, 2011
Filed:

Mar 1, 2010
Appl. No.:

12/715254
Inventors:

Yu Zhao - San Diego CA, US
Babak Nejati - San Diego CA, US
Nathan M Pletcher - Encinitas CA, US
Aristotele Hadjichristos - San Diego CA, US
Assignee:

QUALCOMM, Incorporated - San Diego CA
International Classification:

H03F 3/04
US Classification:

330310, 330302
Abstract:

A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus includes a first active circuit (e. g. , a driver amplifier), a second active circuit (e. g. , a power amplifier), and a tunable inter-stage matching circuit coupled between the first and second active circuits. The tunable inter-stage matching circuit includes a tunable capacitor that can be varied in discrete steps to adjust impedance matching between the first and second active circuits. In an exemplary design, the tunable capacitor includes (i) a plurality of capacitors coupled in parallel and (ii) a plurality of switches coupled to the plurality of capacitors, one switch for each capacitor. Each switch may be turned on to select an associated capacitor or turned off to unselect the associated capacitor. The tunable capacitor may further include a fixed capacitor coupled in parallel with the plurality of capacitors.

Amplifier Module With Multiple Operating Modes
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US Patent:

8102205, Jan 24, 2012
Filed:

Apr 9, 2010
Appl. No.:

12/757679
Inventors:

Nathan M Pletcher - Encinitas CA, US
Aristotele Hadjichristos - San Diego CA, US
Babak Nejati - San Diego CA, US
Assignee:

QUALCOMM, Incorporated - San Diego CA
International Classification:

H03F 1/14
US Classification:

330 51, 330302
Abstract:

An amplifier module with multiple operating modes is described. In an exemplary design, the amplifier module includes an amplifier (e. g. , a power amplifier), a switch, and an output circuit. The amplifier receives and amplifies an input signal and provides an amplified signal in a first mode. The switch is coupled to the output of the amplifier and bypasses the amplifier and provides a bypass signal in a second mode. The output circuit is coupled to the amplifier and the switch. The output circuit performs output impedance matching for the amplifier in the first mode. The output circuit also (i) receives the amplified signal and provides an output signal in the first mode and (ii) receives the bypass signal and provides the output signal in the second mode. The amplifier is enabled in the first mode and disabled in the second mode.

Output Circuit With Integrated Impedance Matching, Power Combining And Filtering For Power Amplifiers And Other Circuits
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US Patent:

8432237, Apr 30, 2013
Filed:

Aug 14, 2009
Appl. No.:

12/541831
Inventors:

Guy Klemens - San Diego CA, US
Nathan M Pletcher - Encinitas CA, US
Babak Nejati - San Diego CA, US
Norman L Frederick - Vista CA, US
Thomas A Myers - San Diego CA, US
Assignee:

QUALCOMM, Incorporated - San Diego CA
International Classification:

H01P 5/12
H03H 7/38
US Classification:

333126, 333129, 333132
Abstract:

An output circuit with integrated impedance matching, power combining, and filtering and suitable for use with power amplifiers and other circuits is described. In an exemplary design, an apparatus may include first and second circuits (e. g. , power amplifiers) and an output circuit. The first circuit may provide a first single-ended signal and may have a first output impedance. The second circuit may provide a second single-ended signal and may have a second output impedance. The output circuit may include (i) first and second matching circuits that perform output impedance matching and filtering for the first and second circuits, (ii) a combiner (e. g. , a summing node) that combines the first and second single-ended signals to obtain a combined single-ended signal, (iii) a third matching circuit that performs impedance matching and filtering for the combined single-ended signal, and (iv) switches to route the single-ended signals to different outputs.

Amplifier Module With Multiple Operating Modes
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US Patent:

8461921, Jun 11, 2013
Filed:

Sep 6, 2011
Appl. No.:

13/226400
Inventors:

Nathan M Pletcher - Encinitas CA, US
Aristotele Hadjichristos - San Diego CA, US
Babak Nejati - San Diego CA, US
Assignee:

QUALCOMM, Incorporated - San Diego CA
International Classification:

H03F 1/14
US Classification:

330 51, 330302
Abstract:

An amplifier module with multiple operating modes is described. In an exemplary design, an apparatus includes a plurality of amplifiers. The apparatus may also include a plurality of switches, each switch coupled to an output of an associated amplifier in the plurality of amplifiers and configured to provide an amplified signal in a first mode and bypass the associated amplifier and provide an associated bypass signal in a second mode. Further, the apparatus may include an output circuit including a plurality of matching circuits, each matching circuit coupled to an associated amplifier in the plurality of amplifiers and an associated switch in the plurality of switches.

Multi-Stage Impedance Matching
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US Patent:

8536950, Sep 17, 2013
Filed:

Dec 17, 2009
Appl. No.:

12/641228
Inventors:

Babak Nejati - San Diego CA, US
Yu Zhao - San Diego CA, US
Nathan M Pletcher - Encinitas CA, US
Aristotele Hadjichristos - San Diego CA, US
Puay Hoe See - San Diego CA, US
Assignee:

QUALCOMM Incorporated - San Diego CA
International Classification:

H03F 3/04
US Classification:

330302, 330 51
Abstract:

Exemplary techniques for performing impedance matching are described. In an exemplary embodiment, the apparatus may include an amplifier (e. g. , a power amplifier) coupled to first and second matching circuits. The first matching circuit may include multiple stages coupled to a first node and may provide input impedance matching for the amplifier. The second matching circuit may include multiple stages coupled to a second node and may provide output impedance matching for the amplifier. At least one switch may be coupled between the first and second nodes and may bypass or select the amplifier. The first and second nodes may have a common impedance. The apparatus may further include a second amplifier coupled in parallel with the amplifier and further to the matching circuits. The second matching circuit may include a first input stage coupled to the amplifier, a second input stage coupled to the second amplifier, and a second stage coupled to the two input stages via switches.

Linear And Polar Dual Mode Transmitter Circuit
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US Patent:

8599938, Dec 3, 2013
Filed:

Nov 25, 2008
Appl. No.:

12/277913
Inventors:

Chiewcharn Narathong - Laguna Niguel CA, US
Ravi Sridhara - San Diego CA, US
Babak Nejati - San Diego CA, US
Assignee:

QUALCOMM Incorporated - San Diego CA
International Classification:

H04L 27/00
US Classification:

375259, 375261, 375298
Abstract:

Method and apparatus for configuring a transmitter circuit to support linear or polar mode. In the linear mode, a baseband signal is specified by adjusting the amplitudes of in-phase (I) and quadrature (Q) signals, while in the polar mode, the information signal is specified by adjusting the phase of a local oscillator (LO) signal and the amplitude of either an I or a Q signal. In an exemplary embodiment, two mixers are provided for both linear and polar mode, with a set of switches selecting the appropriate input signals provided to one of the mixers based on whether the device is operating in linear or polar mode. In an exemplary embodiment, each mixer may be implemented using a scalable architecture that efficiently adjusts mixer size based on required transmit power.

Multi-Antenna Wireless Device With Power Combining Power Amplifiers
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US Patent:

8634782, Jan 21, 2014
Filed:

Oct 14, 2011
Appl. No.:

13/274256
Inventors:

Bhushan Shanti Asuri - San Diego CA, US
Babak Nejati - San Diego CA, US
Assignee:

QUALCOMM Incorporated - San Diego CA
International Classification:

H04M 1/00
US Classification:

455101, 4555521
Abstract:

A wireless device with power combining power amplifiers to support transmission on multiple antennas is disclosed. The power amplifiers may be operated together to obtain higher output power or separately to support transmission on multiple antennas. In an exemplary design, an apparatus includes first and second power amplifiers. The first power amplifier amplifies a first input signal and provides a first output signal for a first antenna in a first operating mode (e. g. , a MIMO mode or a transmit diversity mode). The second power amplifier amplifies the first input signal or a second input signal and provides a second output signal for a second antenna in the first operating mode. The first and second power amplifiers are power combined in a second operating mode to provide a third output signal, which has a higher maximum output power than the first or second output signal.