Baosuo Zhou

US Patent:

7659208, Feb 9, 2010

Filed:

Dec 6, 2007

Appl. No.:

11/952017

Inventors:

Baosuo Zhou - Boise ID, US
Gurtej S. Sandhu - Boise ID, US
Ardavan Niroomand - Boise ID, US

Assignee:

Micron Technology, Inc - Boise ID

International Classification:

H01L 21/311

US Classification:

438700, 257E21626, 257E21627, 257E2164

Abstract:

Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.

US Patent:

7662718, Feb 16, 2010

Filed:

Mar 9, 2006

Appl. No.:

11/372825

Inventors:

Mirzafer K. Abatchev - Boise ID, US
Krupakar Murali Subramanian - Boise ID, US
Baosuo Zhou - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/302

US Classification:

438689, 438725, 438736, 257E2102

Abstract:

Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.

US Patent:

7732343, Jun 8, 2010

Filed:

May 3, 2007

Appl. No.:

11/744074

Inventors:

Ardavan Niroomand - Boise ID, US
Baosuo Zhou - Boise ID, US
Ramakanth Alapati - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/302

US Classification:

438725, 438706, 257E21038, 257E21039

Abstract:

A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

US Patent:

7807575, Oct 5, 2010

Filed:

Nov 29, 2006

Appl. No.:

11/606613

Inventors:

Baosuo Zhou - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 23/544
H01L 21/311

US Classification:

438696, 257797, 257E23179, 257E21249

Abstract:

A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. A partially fabricated integrated circuit device is also disclosed.

US Patent:

7902074, Mar 8, 2011

Filed:

Apr 7, 2006

Appl. No.:

11/400603

Inventors:

Ardavan Niroomand - Boise ID, US
Baosuo Zhou - Boise ID, US
Ramakanth Alapati - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/311

US Classification:

438702, 438694, 438695, 438699, 438703

Abstract:

A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region. The method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.

US Patent:

7910483, Mar 22, 2011

Filed:

Feb 2, 2010

Appl. No.:

12/698407

Inventors:

Mirzafer K Abatchev - Boise ID, US
Krupaker Murali Subramanian - Tewksbury MA, US
Baosuo Zhou - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/302

US Classification:

438689, 438725, 438736, 257E2102

Abstract:

Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.

US Patent:

8011090, Sep 6, 2011

Filed:

May 19, 2008

Appl. No.:

12/123021

Inventors:

Mirzafer Abatchev - Boise ID, US
David Wells - Boise ID, US
Baosuo Zhou - Boise ID, US
Krupakar M. Subramanian - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H05K 3/02
H05K 3/10

US Classification:

29846, 29856, 29858, 29885, 216 39, 216 41, 257546, 257548, 257692, 438106, 438111, 438424, 438427, 438692

Abstract:

Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

US Patent:

8030217, Oct 4, 2011

Filed:

Apr 30, 2010

Appl. No.:

12/771951

Inventors:

Ardavan Niroomand - Boise ID, US
Baosuo Zhou - Boise ID, US
Ramakanth Alapati - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/302

US Classification:

438725, 438706, 438694, 438699, 438695, 438702, 438703

Abstract:

A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.