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Baosuo Zhou

age ~70

from Redwood City, CA

Also known as:
  • Baosuo Zhu
  • O Zhou
  • Baosuo Zhoh
  • Lindy Sherwood-Coombs

Baosuo Zhou Phones & Addresses

  • Redwood City, CA
  • San Mateo, CA
  • Boise, ID
  • Goleta, CA
  • Richardson, TX
  • 846 Lakeshore Dr, Redwood City, CA 94065

Work

  • Company:
    Lam research
    Sep 2011 to 2012
  • Position:
    Process engineer staff

Education

  • School / High School:
    The University of Texas at Dallas
    2001 to 2004

Skills

Silicon • Thin Films • Semiconductors • Design of Experiments • Process Integration • CMOS • JMP • CVD • Device Characterization • Photolithography

Industries

Semiconductors

Us Patents

  • Method For Forming High Density Patterns

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  • US Patent:
    7659208, Feb 9, 2010
  • Filed:
    Dec 6, 2007
  • Appl. No.:
    11/952017
  • Inventors:
    Baosuo Zhou - Boise ID,
    Gurtej S. Sandhu - Boise ID,
    Ardavan Niroomand - Boise ID,
  • Assignee:
    Micron Technology, Inc - Boise ID
  • International Classification:
    H01L 21/311
  • US Classification:
    438700, 257E21626, 257E21627, 257E2164
  • Abstract:
    Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.
  • Methods For Integrated Circuit Fabrication With Protective Coating For Planarization

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  • US Patent:
    8479384, Jul 9, 2013
  • Filed:
    Aug 11, 2011
  • Appl. No.:
    13/207627
  • Inventors:
    Mirzafer Abatchev - Boise ID,
    David Wells - Boise ID,
    Baosuo Zhou - Boise ID,
    Krupakar M. Subramanian - Boise ID,
  • Assignee:
    Micron Technology, Inc. - Boise ID
  • International Classification:
    H05K 3/20
  • US Classification:
    29831, 29841, 29846, 29856, 29883, 216 39, 216 41, 257546, 257548, 257692, 438106, 438111, 438424, 438427, 438692
  • Abstract:
    Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
  • Methods For Integrated Circuit Fabrication With Protective Coating For Planarization

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  • US Patent:
    2013029, Nov 7, 2013
  • Filed:
    Jul 5, 2013
  • Appl. No.:
    13/936086
  • Inventors:
    David Wells - Boise ID,
    Baosuo ` Zhou - Boise ID,
    Krupakar Murali Subramanian - Boise ID,
  • International Classification:
    H01L 21/306
  • US Classification:
    438692, 438696
  • Abstract:
    Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
  • Simplified Pitch Doubling Process Flow

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  • US Patent:
    2013010, May 2, 2013
  • Filed:
    Dec 21, 2012
  • Appl. No.:
    13/725915
  • Inventors:
    Micron Technology, Inc. - Boise ID,
    Baosuo Zhou - Redwood City CA,
    Ramakanth Alapati - Boise ID,
  • Assignee:
    MICRON TECHNOLOGY, INC. - Boise ID
  • International Classification:
    H01L 27/04
  • US Classification:
    257499
  • Abstract:
    A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
  • Methods To Reduce The Critical Dimension Of Semiconductor Devices And Related Semiconductor Devices

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  • US Patent:
    2013000, Jan 10, 2013
  • Filed:
    Sep 14, 2012
  • Appl. No.:
    13/619905
  • Inventors:
    Baosuo Zhou - Boise ID,
  • Assignee:
    MICRON TECHNOLOGY, INC. - Boise ID
  • International Classification:
    H01L 29/06
    H01L 21/311
  • US Classification:
    257618, 438696, 257E29005, 257E21249
  • Abstract:
    A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. Integrated circuit devices are also disclosed.
  • Methods Of Forming Patterns On Substrates

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  • US Patent:
    2010029, Nov 18, 2010
  • Filed:
    May 18, 2009
  • Appl. No.:
    12/467687
  • Inventors:
    Baosuo Zhou - Boise ID,
    Alex J. Schrinsky - Boise ID,
  • International Classification:
    H01L 21/3065
  • US Classification:
    438710, 257E21218, 438591
  • Abstract:
    Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the carbon-comprising material. Etching is conducted only partially into the carbon-comprising material and spaced second features are formed within the carbon-comprising material which comprise the partially etched carbon-comprising material. Spacers can be formed along sidewalls of the spaced second features. The carbon-comprising material can be etched through to the base material using the spacers as a mask. Spaced third features can be formed which comprise the anisotropically etched spacers and the carbon-comprising material.
  • Pitch Reduction Technology Using Alternating Spacer Depositions During The Formation Of A Semiconductor Device And Systems Including Same

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  • US Patent:
    2008000, Jan 10, 2008
  • Filed:
    Jul 10, 2006
  • Appl. No.:
    11/484271
  • Inventors:
    Baosuo Zhou - Boise ID,
    Mirzafer K. Abatchev - Boise ID,
    Ardavan Niroomand - Boise ID,
    Paul A. Morgan - Kuna ID,
    Shuang Meng - Boise ID,
    Joseph N. Greeley - Boise ID,
    Brian J. Coppa - Boise ID,
  • International Classification:
    G03F 7/26
  • US Classification:
    430313, 430311
  • Abstract:
    A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
  • Etch Process Used During The Manufacture Of A Semiconductor Device And Systems Including The Semiconductor Device

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  • US Patent:
    2007012, May 31, 2007
  • Filed:
    Nov 14, 2005
  • Appl. No.:
    11/272980
  • Inventors:
    Baosuo Zhou - Boise ID,
    Mirzafer Abatchev - Boise ID,
    Krupakar Subramanian - Boise ID,
  • International Classification:
    C23F 1/00
    H01L 29/04
    H01L 21/461
    B44C 1/22
    H01L 31/036
  • US Classification:
    438706000, 216041000, 216078000, 257049000
  • Abstract:
    A carbon or carbon-containing underlayer, which is used as a mask, is patterned using a process comprising, in one specific embodiment, boron trichloride and oxygen under specified processing conditions to etch the underlayer. The underlayer is then used as a mask to etch a layer below the underlayer, such as a semiconductor wafer or a layer formed as part of a semiconductor wafer substrate assembly. Various processing conditions are described, as is the formation of various features using embodiments of the inventive process.

Resumes

Baosuo Zhou Photo 1

Baosuo Zhou

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Position:
Process Engineer Staff at Lam Research
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Lam Research since Sep 2011
Process Engineer Staff

Micron Technology/USA Feb 2009 - Sep 2011
Senior engineer

Micron 2005 - 2009
Process engineer
Education:
The University of Texas at Dallas 2001 - 2004
University of California, Santa Barbara 1999 - 2001
Institute of Physics, Chinese Academy of Sciences 1993 - 1996
Skills:
Silicon
Thin Films
Semiconductors
Design of Experiments
Process Integration
CMOS
JMP
CVD
Device Characterization
Photolithography

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Baosuo Zhou

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Baosuo Zhou Photo 3

Baosuo Zhou Goleta CA

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