Barry W Herold

US Patent:

6573782, Jun 3, 2003

Filed:

Jan 26, 2001

Appl. No.:

09/769941

Inventors:

Barry Herold - Barrington IL
Scott Humphreys - Greensboro NC

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03D 302

US Classification:

329315, 329336, 329327, 329318, 329340, 455214, 455337, 455334

Abstract:

A circuit ( ) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector ( ) and a sigma-delta analog-to-digital converter ( ). The FM ratio detector ( ) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter ( ), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic â1sâ and logic â0sâ that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal ( ).

US Patent:

6667769, Dec 23, 2003

Filed:

Dec 10, 2001

Appl. No.:

10/012947

Inventors:

Austin Harton - Oak Park IL
Francisco Castro - St. Charles IL
Barry Herold - Barrington IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04N 314

US Classification:

348308, 348297, 348302

Abstract:

A time-integrating pixel sensor having a photo-detector, a capacitor, a comparator and a pixel data buffer. In operation, the photo-current from the photo-detector charges the capacitor and produces a photo-voltage. The photo-voltage sensed by the capacitor and a reference voltage is compared with the comparator. If the photo-voltage exceeds the reference voltage, a global code value is latched into the pixel data buffer. The optical power falling on the photo-detector is determined from the latched code value. An array of sensors is incorporated into a semiconductor device together with circuitry to read and decode the pixel data buffers. The reference voltage may be varied in time to increase the dynamic range of the sensor.

US Patent:

6704046, Mar 9, 2004

Filed:

Apr 17, 2002

Appl. No.:

10/124381

Inventors:

Robert Dyas - Naperville IL
Francisco Castro - Saint Charles IL
Austin Harton - Oak Park IL
Barry Herold - Barrington IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04N 973

US Classification:

3482231, 348297, 348308, 2502081

Abstract:

A pixel image sensor having an array of pixel elements arranged in a color mosaic pattern, each pixel element being responsive to light of a particular color. Each pixel element is supplied with a reference voltage signal corresponding to the color of light to which the pixel element is responsive. The reference voltage signal determined the sensitivity of the pixel element. The white balance of the image sensor is adjusted by varying independently the reference voltage signals for each color. The color mosaic pattern of the array may include a pixel element responsive to white light. The output from the white pixel sensors may be used to adjust the color constancy of the image sensor. The image array reduces the need for post-capture processing of the image for white balancing, by incorporating the white balance operation into the capture process.

US Patent:

6888573, May 3, 2005

Filed:

Oct 31, 2002

Appl. No.:

10/285250

Inventors:

Barry W. Herold - Barrington IL, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04N003/14
H04N009/64
H01L027/148
H01L029/768

US Classification:

348314, 348308, 348248, 257223, 257230, 257445

Abstract:

An anti-blooming charge accumulation pixel using an anti-blooming element coupled to the pixel prevents blooming by ensuring that a voltage of a charge accumulation device of the pixel is always returned to a clamping voltage following comparison events. The anti-blooming element is used to return the voltage across a photodiode to the supply voltage when both a low voltage comparison and a high voltage comparison have occurred. A control block is used to determine an input signal to the anti-blooming element based upon the result of a low voltage comparison and a high voltage comparison. The input signal can be used to drive the anti-blooming element to a desired logic level, thereby causing the voltage across the charge accumulation device to be the clamping voltage. The use of the anti-blooming element eliminates blooming to adjacent pixels, independent of an integration time of the pixel.

US Patent:

7176970, Feb 13, 2007

Filed:

Jun 30, 2003

Appl. No.:

10/609853

Inventors:

King F. Lee - Schaumburg IL, US
Austin Harton - Oak Park IL, US
Barry W. Herold - Barrington IL, US
Bei Tang - Schaumburg IL, US

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04N 5/335

US Classification:

348297, 348308

Abstract:

A photodetector () generates an electrical signal that has a value that changes approximately linearly at a rate that is proportional to an amount of light intensity incident on a photodetector since a most recent reset command was received at a reset input of the photodetector. A measurement circuit () generates a comparison state that is based on a comparison of the value of the photodetector signal to a reference signal in response to one of a plurality a sample pulses. A control circuit () generates the plurality of sample pulses at non-uniform time intervals and generates an elapsed time as an accumulation of the non-uniform time intervals occurring from the reset command to a change of the comparison state. In one embodiment, the reciprocal of an accumulated duration of the non-uniform time intervals is a linear function of a number of time intervals after the reset command.

US Patent:

20020127757, Sep 12, 2002

Filed:

Mar 8, 2001

Appl. No.:

09/801881

Inventors:

Steven Gillig - Roselle IL, US
Barry Herold - Barrington IL, US

Assignee:

MOTOROLA, INC

International Classification:

H01L021/00
H01L021/84

US Classification:

438/046000, 438/106000

Abstract:

A composite integrated circuit with electrical isolation is provided. The composite integrated circuit includes a Group IV semiconductor portion and a compound semiconductor portion. The composite integrated circuit includes electrical signal processing circuitry that is formed at least partly from the Group IV semiconductor portion. The composite integrated circuit includes circuitry that allows the processing circuitry to communicate via an electrical connection with the external circuitry and an optical connection that is provided by a pair of optical components that are at least partly formed in the compound semiconductor portion. The optical connection electrically insulates the processing circuitry from electrical signals in the electrical connection.

US Patent:

20020175334, Nov 28, 2002

Filed:

May 22, 2001

Appl. No.:

09/861637

Inventors:

Barry Herold - Barrington IL, US

Assignee:

MOTOROLA, INC. - Schaumburg IL

International Classification:

H01L027/15
H01L031/12

US Classification:

257/080000, 257/085000

Abstract:

Composite integrated circuits and methods for processing RF input signals are provided. A Bragg cell structure having a waveguide sample and a piezoelectric that may be used for surface acoustic waves is shown. The Bragg cell structure may be combined with other circuitry that may be produced from a monocrystalline-based material or from a compound semiconductor material in a composite integrated circuit. Such other circuitry may include an amplifier, a photoemitter, a photodetector array, an analog to digital converter, and a digital signal processor.

US Patent:

20020175347, Nov 28, 2002

Filed:

May 22, 2001

Appl. No.:

09/861639

Inventors:

Barry Herold - Barrington IL, US

Assignee:

MOTOROLA, INC. - Schaumburg IL

International Classification:

H01L031/0328

US Classification:

257/195000

Abstract:

A hybrid integrated circuit includes a monocrystalline accommodating layer positioned between a monocrystalline substrate and a compound semi-conductor layer. Electronic circuitry may be embedded in both the monocrystalline substrate and the compound semiconductor layer. Internal circuitry may be formed in either of these regions while an associated I/O structure is formed in the other region. Use of the invention allows circuits that are formed using either structure to easily communicate with external devices that are more suited for communication with circuits that are formed using another structure.