Barry A Wagner

US Patent:

6362997, Mar 26, 2002

Filed:

Oct 16, 2000

Appl. No.:

09/690170

Inventors:

Larry Fiedler - Mountain View CA
Simon Thomas - Campbell CA
Barry Wagner - San Jose CA

Assignee:

nVIDIA - Santa Clara CA

International Classification:

H01L 2348

US Classification:

365 63, 365 51, 257723, 257724, 361720, 361722, 361736, 361748, 361751, 361760, 361777

Abstract:

A memory system is disclosed. The memory system comprises a circuit board and at least two memory devices mounted on the circuit board. Each of the at least two memory devices includes a plurality of pins for receiving and providing signals. At least a first portion of the pins of one of the at least two memory devices are coupled to at least a second portion of the pins of the other at least two memory devices such that a pair of the first portion coupled to a pin of the second portion forms a coupled load. The coupled load then appears as one load. Accordingly, in a system in accordance with the present invention, at least two memory devices are provided on a circuit board. Each of the at least two memory devices includes a plurality of pins. At least a portion of the pins of one of the two memory devices is in close proximity to and coupled to the at least a portion of the pins of the other of the at least two memory devices such that a pin and one memory device is coupled to a pin on the other memory device to form a coupled load. The coupled load then appears as one load.

US Patent:

6496404, Dec 17, 2002

Filed:

Nov 6, 2001

Appl. No.:

09/993105

Inventors:

Larry Fiedler - Mountain View CA
Simon Thomas - Campbell CA
Barry Wagner - San Jose CA

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

H01L 2348

US Classification:

365 63, 365 51, 257723, 257724, 257722

Abstract:

A memory system is disclosed. The memory system comprises a circuit board and at least two memory devices mounted on the circuit board. Each of the at least two memory devices includes a plurality of pins for receiving and providing signals. At least a first portion of the pins of one of the at least two memory devices are coupled to at least a second portion of the pins of the other at least two memory devices such that a pair of the first portion coupled to a pin of the second portion forms a coupled load. The coupled load then appears as one load. Accordingly, in a system in accordance with the present invention, at least two memory devices are provided on a circuit board. Each of the at least two memory devices includes a plurality of pins. At least a portion of the pins of one of the two memory devices is in close proximity to and coupled to the at least a portion of the pins of the other of the at least two memory devices such that a pin and one memory device is coupled to a pin on the other memory device to form a coupled load. The coupled load then appears as one load.

US Patent:

6947865, Sep 20, 2005

Filed:

Feb 15, 2002

Appl. No.:

10/078292

Inventors:

Ludger Mimberg - San Jose CA, US
Barry Wagner - San Jose CA, US
Mau Lao - San Jose CA, US

Assignee:

nVIDIA Corporation - Santa Clara CA

International Classification:

G01K001/00

US Classification:

702130, 702 64

Abstract:

A processor power supply voltage controller. The controller includes a temperature sensor configured to sense a temperature of a processor and generate a temperature signal in accordance therewith. A regulator is coupled to provide a power supply voltage to the processor. The regulator is coupled to receive the temperature signal and control the power supply voltage to maintain a substantially stable crosstalk level within the processor.

US Patent:

7315957, Jan 1, 2008

Filed:

Dec 18, 2003

Appl. No.:

10/742444

Inventors:

Barry Wagner - San Jose CA, US
Jonah M. Alben - San Jose CA, US
Sonny Yeoh - San Jose CA, US
Jeffrey J. Irwin - Sunnyvale CA, US
Saurabh Gupta - Santa Clara CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 1/00

US Classification:

713501, 713500, 713502

Abstract:

Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selected to provide a memory clock signal to the graphics memory. The multiplexer switches from providing a first clock source signal as the memory clock signal to providing a second clock source signal as the memory clock signal. The first clock source changes its frequency of operation. After the first clock source settles or stabilizes, the multiplexer switches back to providing the first clock source signal as the memory clock signal.

US Patent:

7370170, May 6, 2008

Filed:

Aug 3, 2004

Appl. No.:

10/910050

Inventors:

Ashfaq R. Shaikh - San Jose CA, US
Barry A. Wagner - San Jose CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711167, 710 52, 710 58, 345563, 345626

Abstract:

Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the WRITE-TRAINING mode is asserted the memory data mask (DM) pin is converted to an output port. Incoming WRITE data is strobed-into the memory device and the resulting data pattern is compared to a desired pattern. If the incoming WRITE data and strobed-in data match, that result is sent to the graphical processing system by setting the DM pin HIGH. If the incoming WRITE data and the strobed-in data do not match, that result is sent to the graphical processing system by setting the DM pin LOW. Beneficially, the incoming data and the desired pattern are derived from pseudo random bit sequence (PRBS) sources.

US Patent:

7447848, Nov 4, 2008

Filed:

Jan 4, 2006

Appl. No.:

11/326157

Inventors:

Barry Wagner - San Jose CA, US

International Classification:

G06F 13/28

US Classification:

711154, 711100, 711105, 711157

Abstract:

Embodiments for retrieving data from memory devices using sub-partitioned addresses are disclosed.

US Patent:

7477257, Jan 13, 2009

Filed:

Dec 15, 2005

Appl. No.:

11/303187

Inventors:

Joseph David Greco - San Jose CA, US
Jonah M. Alben - San Jose CA, US
Barry A. Wagner - San Jose CA, US
Anthony Michael Tamasi - Los Gatos CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G09G 5/39
G06F 13/28
G06F 13/00
G06F 13/14

US Classification:

345531, 345533, 345536, 345520, 711111, 711154

Abstract:

A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub.

US Patent:

7519892, Apr 14, 2009

Filed:

Oct 14, 2005

Appl. No.:

11/251405

Inventors:

Russell R. Newcomb - Morgan Hill CA, US
William B. Simms - San Jose CA, US
Barry A. Wagner - San Jose CA, US

Assignee:

nVidia Corporation - Santa Clara CA

International Classification:

H03M 13/00

US Classification:

714758, 369 5913

Abstract:

Embodiments for binary encoding and/or decoding data are disclosed. In or more embodiments, N data bits may be encoded using one of a plurality of codes derived from at least N+1 bits wherein each of the plurality of codes comprises approximately equal numbers of bits at a first logical level and a second logical level.