Bassam Jamil Mohd

US Patent:

7902878, Mar 8, 2011

Filed:

Apr 29, 2009

Appl. No.:

12/431992

Inventors:

Martin Saint-Laurent - Austin TX, US
Bassam Jamil Mohd - Austin TX, US
Paul Bassett - Austin TX, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03K 19/096

US Classification:

326 98, 326 95

Abstract:

A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.