Becky P Losee

US Patent:

6916745, Jul 12, 2005

Filed:

May 20, 2003

Appl. No.:

10/442670

Inventors:

Robert Herrick - Lehi UT, US
Becky Losee - Cedar Hills UT, US
Dean Probst - West Jordan UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L021/311

US Classification:

438700, 438672, 438270, 438274, 257774

Abstract:

In accordance with an embodiment of the present invention, a semiconductor device is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer. Additional exposed surface areas of the silicon layer where silicon can be removed are defined. Additional portions of the silicon layer are removed to form outer sections of the trench such that the outer sections of the trench extend into the silicon layer from the additional exposed surface areas of the silicon layer. The middle section of the trench extends deeper into the silicon layer than the outer sections of the trench.

US Patent:

7078296, Jul 18, 2006

Filed:

Jan 16, 2002

Appl. No.:

10/052234

Inventors:

Duc Chau - San Jose CA, US
Becky Losee - Cedar Hills UT, US
Bruce Marchant - Murray UT, US
Dean Probst - West Jordan UT, US
Robert Herrick - Lehi UT, US
James Murphy - South Jordan UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/8232

US Classification:

438270, 438589, 438667, 438675, 438695, 438700, 438760

Abstract:

Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOSFET is provided by making the sidewall of the overlying isolation dielectric layer substantially aligned with the sidewall of the gate conductor. Such an alignment can be made through any number of methods such as using a dual dielectric process, using a selective dielectric oxidation process, using a selective dielectric deposition process, or a spin-on-glass dielectric process.

US Patent:

7344943, Mar 18, 2008

Filed:

Apr 20, 2005

Appl. No.:

11/111305

Inventors:

Robert Herrick - Lehi UT, US
Becky Losee - Cedar Hills UT, US
Dean Probst - West Jordan UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/336

US Classification:

438259, 438270, 438274, 257330

Abstract:

A semiconductor device is formed as follows. A plurality of trenches is formed in a silicon layer. An insulating layer filling an upper portion of each trench is formed. Exposed silicon is removed from adjacent the trenches to expose an edge of the insulating layer in each trench, such that the exposed edge of the insulating layer in each trench defines a portion of each contact opening formed between every two adjacent trenches.

US Patent:

7595524, Sep 29, 2009

Filed:

Mar 17, 2008

Appl. No.:

12/049996

Inventors:

Robert Herrick - Lehi UT, US
Becky Losee - Cedar Hills UT, US
Dean Probst - West Jordan UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 29/94

US Classification:

257302, 257330, 257331, 257332, 257905, 257E2926, 257E29201, 257E29257, 257E27091

Abstract:

A field effect transistor includes a plurality of trenches extending into a silicon layer. Each trench has upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches, and source regions extend in the body regions adjacent opposing sidewalls of each trench. The source regions have a conductivity type opposite that of the body regions.

US Patent:

7799636, Sep 21, 2010

Filed:

Sep 25, 2009

Appl. No.:

12/567578

Inventors:

Robert Herrick - Lehi UT, US
Becky Losee - Cedar Hills UT, US
Dean Probst - West Jordan UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/336

US Classification:

438259, 438242, 438270, 438561, 438700, 257E21549, 257E27091, 257E29257, 257E2926

Abstract:

A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and outer portions extending directly underneath the masking layer. The outer portions form outer sections of corresponding trenches. Additional portions of the silicon layer are removed through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches. A first doped region of a first conductivity type is formed in an upper portion of the silicon layer. An insulating layer is formed within each trench, and extends directly over a portion of the first doped region adjacent each trench sidewall. Silicon is removed from adjacent each trench until, of the first doped region, only the portions adjacent the trench sidewalls remain.

US Patent:

8034682, Oct 11, 2011

Filed:

Sep 16, 2010

Appl. No.:

12/884072

Inventors:

Robert Herrick - Lehi UT, US
Becky Losee - Cedar Hills UT, US
Dean Probst - West Jordan UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/8242
H01L 21/336

US Classification:

438242, 438259, 438270, 438561, 257E21549, 257E27091, 257E29257, 257E2926

Abstract:

A method of forming a semiconductor device includes the following. Removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer; and forming source regions in the silicon layer adjacent the trench sidewall such that the source regions extend into the portions of the silicon layer directly over which the trench sidewalls extend.

US Patent:

8143123, Mar 27, 2012

Filed:

Mar 3, 2008

Appl. No.:

12/041546

Inventors:

Thomas E. Grebs - Mountaintop PA, US
Rodney S. Ridley - Mountaintop PA, US
Steven P. Sapp - Felton PA, US
Peter H. Wilson - Wrightwood CA, US
Babak S. Sani - Oakland CA, US
Gary M. Dolny - Mountaintop PA, US
John Mytych - Mohnton PA, US
Becky Losee - Cedar Hills UT, US
Adam Selsley - Mountaintop PA, US
Christopher B. Kocon - Plains PA, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/336

US Classification:

438259, 438283, 438270, 257E21019, 257341

Abstract:

A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.

US Patent:

8143124, Mar 27, 2012

Filed:

Feb 15, 2008

Appl. No.:

12/032599

Inventors:

Ashok Challa - Sandy UT, US
Alan Elbanhawy - Hollister CA, US
Dean E. Probst - West Jordan UT, US
Steven P. Sapp - Felton CA, US
Peter H. Wilson - Wrightwood CA, US
Babak S. Sani - Oakland CA, US
Becky Losee - Cedar Hills UT, US
Robert Herrick - Lehi UT, US
James J. Murphy - South Jordan UT, US
Gordon K. Madson - Riverton UT, US
Bruce D. Marchant - Murray UT, US
Christopher B. Kocon - Plains PA, US
Debra S. Woolsey - Draper UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 29/78
H01L 21/336

US Classification:

438270, 257341, 257E27091, 257E29201, 257E29257, 257E21655

Abstract:

A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a charge control trench extending deeper into the drift region than the active trench, an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate, an electrode in the active trench, and source regions. The method also includes etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench.