Jente Benedict Kuang

US Patent:

6373281, Apr 16, 2002

Filed:

Jan 22, 2001

Appl. No.:

09/767218

Inventors:

Jente Benedict Kuang - Lakeville MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 1900

US Classification:

326 58, 326 33, 326 34

Abstract:

A method and apparatus are provided for tri-state dynamic body charge modulation for sensing devices in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) applications. A sense amplifier includes a silicon-on-insulator (SOI) field effect transistor. A tri-state body charge modulation circuit is coupled to a body of the silicon-on-insulator (SOI) field effect transistor. The body charge modulation circuit provides a high body bias preparatory state; a floating body state and a low body bias stand-by state enabling high performance operation, good matching characteristics, and low stand-by leakage suitable for low-power applications. The tri-state body charge modulation circuit includes a P-channel field effect transistor (PFET) and an N-channel field effect transistor (NFET) connected between a high voltage potential and ground. The junction of the series connected PFET and NFET is coupled to the SOI FET body for providing a charging path to a high power supply voltage rail and a discharging path to ground and a high impedance state.

US Patent:

6392855, May 21, 2002

Filed:

Aug 14, 2000

Appl. No.:

09/638254

Inventors:

Jente Benedict Kuang - Lakeville MN
Mary Joseph Saccamango - Poughquag NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 900

US Classification:

361 56, 361 911, 361111, 361118

Abstract:

Methods and apparatus are provided for monitoring excess body charges in partially depleted SOI CMOS devices. An apparatus for floating body charge monitoring in partially depleted silicon-on-insulator (SOI) CMOS circuits includes a monitor core circuit for conditionally generating an intentional bipolar discharge current. A current mirroring multiplier is coupled to the monitor core circuit for amplifying the intentional bipolar discharge current and generating a state disturb current. A state setting latch is coupled to the current mirroring multiplier for determining and setting a condition for a discharge action.

US Patent:

6404686, Jun 11, 2002

Filed:

Jan 26, 2001

Appl. No.:

09/770912

Inventors:

Anthony Gus Aipperspach - Rochester MN
Fariborz Assaderaghi - Mahopac NY
Todd Alan Christensen - Rochester MN
Douglas Michael Dewanz - Rochester MN
Jente Benedict Kuang - Lakeville MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 700

US Classification:

365205, 365203, 365207

Abstract:

A high performance, low cell stress, low-power silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus are provided. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sense amplifier includes a precharge circuit for charging complementary bit and data lines to a predefined precharge voltage during a precharge cycle. The precharge voltage is lower than a full rail voltage. The reduced bit and data line precharge voltage substantially reduces voltage stress applied to the access transistors in the RAM cells. A pre-amplifying mechanism produces an offset voltage between the complementary data lines before the. sense amplifier is set. The pre-amplifying mechanism includes a pre-amplifying FET that is substantially smaller than a sensing silicon-on-insulator (SOI) field effect transistor (FET) in the sense amplifier.

US Patent:

6441663, Aug 27, 2002

Filed:

Nov 2, 2000

Appl. No.:

09/704436

Inventors:

Jente Benedict Kuang - Lakeville MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3037

US Classification:

327206, 327537

Abstract:

A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis and a method are provided for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications. A SOI CMOS Schmitt trigger circuit with controllable hysteresis includes a stack of a plurality of field effect transistors (FETs) connected in series between a voltage supply and ground. An input is applied to a gate of each of the stack of the plurality of field effect transistors (FETs). The stack of the plurality of field effect transistors (FETs) provides an output at a junction of a predetermined pair of the plurality of field effect transistors (FETs). At least one feedback field effect transistor (FET) has a source coupled a junction of a predefined pair of the stack of field effect transistors (FETs) and has a gate coupled to the output. A FET body of each of the stack of the plurality of field effect transistors (FETs) is connected to a voltage supply rail.

US Patent:

6448830, Sep 10, 2002

Filed:

Nov 5, 2001

Appl. No.:

10/007854

Inventors:

Jente Benedict Kuang - Lakeville MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3037

US Classification:

327205

Abstract:

A tri-state Schmitt trigger inverting device having multiple tri-state controller switching devices between a conventional voltage mode Schmitt trigger its voltage supply rails. When an enabling signal to the tri-state controller switching devices is set to a first level, the tri-state Schmitt trigger functions as a standard logic inverter. When a complementary enabling signal is received at the tri-state controller switching devices, the connections to the high voltage rail and low voltage rail of the tri-state Schmitt trigger are turned off, and the output of the tri-state Schmitt trigger is a high impedance. Thus, the device is a single stage tri-state Schmitt inverter having optimal hysteresis characteristics with minimal power consumption.

US Patent:

6504212, Jan 7, 2003

Filed:

Feb 3, 2000

Appl. No.:

09/497361

Inventors:

David Howard Allen - Rochester MN
Jente Benedict Kuang - Lakeville MN
Pong-Fei Lu - Yorktown Heights NY
Mary Joseph Saccamango - Poughquag NY
Daniel Lawrence Stasiak - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2701

US Classification:

257347, 257348, 257351, 257355, 257356, 257547

Abstract:

A method and apparatus are provided for implementing enhanced silicon-on-insulator (SOI) passgate operations. The apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations includes a silicon-on-insulator (SOI) passgate field effect transistor. A select input is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. A discharging field effect transistor of an opposite channel type is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is activated during an off cycle of the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is coupled to the body of the SOI passgate field effect transistor. The discharging field effect transistor is deactivated during an on cycle of the SOI passgate field effect transistor, whereby the body of the SOI passgate field effect transistor floats during the on cycle. The method for implementing enhanced silicon-on-insulator (SOI) passgate operations can be used with N-channel or P-channel implementations as well as with a combination of N-channel and P-channel devices.

US Patent:

6608785, Aug 19, 2003

Filed:

Jan 7, 2002

Appl. No.:

10/041231

Inventors:

Jente Benedict Kuang - Lakeville MN
Mary Joseph Saccamango - Poughquag NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11K 700

US Classification:

365201, 361 56

Abstract:

Methods and apparatus are provided to ensure functionality and timing robustness in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits. A select signal for the SOI CMOS circuit is received. A floating body charge monitoring circuit is coupled to the SOI CMOS circuit for monitoring excess body charges in at least one predefined SOI device and providing an output control signal. A select signal adjusting circuit is coupled to the floating body charge monitoring circuit receiving the output control signal and the select signal and providing a conditionally adjusted select signal responsive to the output control signal of the floating body charge monitor circuit. The conditionally adjusted select signal is applied to the SOI CMOS circuit. The conditionally adjusted select signal provided by the select signal adjusting circuit responsive to the output control signal of the floating body charge monitor circuit includes a predefined delay at the trailing edge of the select signal extending the select signal pulse width.

US Patent:

6635518, Oct 21, 2003

Filed:

Apr 4, 2001

Appl. No.:

09/825704

Inventors:

Anthony Gus Aipperspach - Rochester MN
Jente Benedict Kuang - Lakeville MN
Daniel Lawrence Stasiak - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438151, 438154, 438163, 438175, 438214, 438280, 257347, 257348, 257349, 257354

Abstract:

Methods and apparatus are provided for creating field effect transistor (FET) body connections with high-quality matching characteristics and no area penalty for partially depleted silicon-on-insulator (SOI) circuits. The FET body connections are created for partially depleted silicon-on-insulator (SOI) technologies by forming adjacent FET devices inside a shallow trench shape. The adjacent FET devices share a common diffusion area, such as source or drain. Selectively spacing apart adjacent gate lines form an underpath connecting bodies of the adjacent FET devices. The underpath is defined by forming an undepleted region on top of a buried oxide layer. The adjacent polysilicon gate lines are selectively spaced apart to define a depth of depletion in a shared diffusion region for creating the underpath. Also, adjacent FET devices with connecting bodies can be built by adding an ion implant masking step to the fabrication process. This masking step changes the depletion depth under the shared diffusion area.