Benjamin M Clark

US Patent:

6785785, Aug 31, 2004

Filed:

Jan 25, 2001

Appl. No.:

09/770759

Inventors:

Gary J. Piccirillo - Cypress TX
John M. MacLaren - Cypress TX
Robert A. Lester - Tomball TX
John E. Larson - Houston TX
Jerome J. Johnson - Spring TX
Benjamin H. Clark - Spring TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711157, 711114, 714710, 714763

Abstract:

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.

US Patent:

6832286, Dec 14, 2004

Filed:

Jun 25, 2002

Appl. No.:

10/179081

Inventors:

Jerome J. Johnson - Spring TX
Benjamin H. Clark - Spring TX
Gary J. Piccirillo - Cypress TX
John M. MacLaren - Cypress TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711105, 711167

Abstract:

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). To optimally run back to back cycles to the memory modules, a technique for providing de-rating parameters such that unnecessary latencies designed into the memory devices can be removed while the system is executing requests. By removing any unnecessary latency, cycle time and overall system performance can be improved.

US Patent:

6938133, Aug 30, 2005

Filed:

Sep 28, 2001

Appl. No.:

09/965913

Inventors:

Jerome J. Johnson - Spring TX, US
Benjamin H. Clark - Spring TX, US
Gary J. Piccirillo - Cypress TX, US
John M. MacLaren - Cypress TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F012/00

US Classification:

711158, 710309

Abstract:

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.

US Patent:

7010652, Mar 7, 2006

Filed:

Aug 27, 2004

Appl. No.:

10/928046

Inventors:

Gary J. Piccirillo - Cypress TX, US
John M. MacLaren - Cypress TX, US
Robert A. Lester - Tomball TX, US
John E. Larson - Houston TX, US
Jerome J. Johnson - Spring TX, US
Benjamin H. Clark - Spring TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00

US Classification:

711157, 711114, 714 6, 714764

Abstract:

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.

US Patent:

7028213, Apr 11, 2006

Filed:

Sep 28, 2001

Appl. No.:

09/965883

Inventors:

Tim Majni - The Woodlands TX, US
Gary J. Piccirillo - Cypress TX, US
John M. MacLaren - Cypress TX, US
Robert A. Lester - Tomball TX, US
John E. Larson - Houston TX, US
Jerome J. Johnson - Spring TX, US
Benjamin H. Clark - Spring TX, US
Patrick L. Ferguson - Cypress TX, US
Siamak Tavallaei - Spring TX, US
Jeffrey S. Autor - Houston TX, US
Christian H. Post - Spring TX, US
Dan Fink - Cypress TX, US
Jeffery Galloway - The Woodlands TX, US
Bret D. Roscoe - Tomball TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 5, 714 42

Abstract:

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

US Patent:

7194577, Mar 20, 2007

Filed:

Aug 29, 2003

Appl. No.:

10/652943

Inventors:

Jerome J. Johnson - Spring TX, US
Benjamin H. Clark - Spring TX, US
Gary J. Piccirillo - Cypress TX, US
John M. MacLaren - Cypress TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00

US Classification:

711114, 711167, 714 7

Abstract:

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.

US Patent:

7320086, Jan 15, 2008

Filed:

Dec 1, 2005

Appl. No.:

11/291243

Inventors:

Tim Majni - The Woodlands TX, US
Gary J. Piccirillo - Cypress TX, US
John M. MacLaren - Cypress TX, US
Robert A. Lester - Tomball TX, US
John E. Larson - Houston TX, US
Jerome J. Johnson - Spring TX, US
Benjamin H. Clark - Spring TX, US
Patrick L. Ferguson - Cypress TX, US
Siamak Tavallaei - Spring TX, US
Jeffrey S. Autor - Houston TX, US
Christian H. Post - Spring TX, US
Dan Fink - Cypress TX, US
Jeffery Galloway - The Woodlands TX, US
Bret D. Roscoe - Tomball TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 5, 714 42

Abstract:

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

US Patent:

20040073767, Apr 15, 2004

Filed:

Aug 29, 2003

Appl. No.:

10/652939

Inventors:

Jerome Johnson - Spring TX, US
Benjamin Clark - Spring TX, US
Gary Piccirillo - Cypress TX, US
John MacLaren - Cypress TX, US

International Classification:

G06F012/08

US Classification:

711/202000, 711/114000

Abstract:

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.

Address:

1148 Arlington St, Houston, TX 77008

VIN:

4JGBB86E17A211941

Make:

MERCEDES-BENZ

Model:

M-CLASS

Year:

2007