Benjamin E Marshall

US Patent:

8078833, Dec 13, 2011

Filed:

May 29, 2008

Appl. No.:

12/156006

Inventors:

Xiaolin Wang - Concord MA, US
Qian Wu - San Jose CA, US
Benjamin Marshall - Stow MA, US
Fugui Wang - Sterling MA, US
Ke Ning - Framingham MA, US
Gregory Pitarys - Stow MA, US

Assignee:

Axis Semiconductor, Inc. - Boxborough MA

International Classification:

G06F 15/00
G06F 15/76

US Classification:

712 15, 712229

Abstract:

The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

US Patent:

8181003, May 15, 2012

Filed:

May 29, 2008

Appl. No.:

12/156007

Inventors:

Xiaolin Wang - Concord MA, US
Qian Wu - San Jose CA, US
Benjamin Marshall - Stow MA, US
Fugui Wang - Sterling MA, US
Gregory Pitarys - Stow MA, US
Ke Ning - Framingham MA, US

Assignee:

Axis Semiconductor, Inc. - Boxborough MA

International Classification:

G06F 9/30

US Classification:

712225, 712 11, 712220

Abstract:

Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

US Patent:

20030120894, Jun 26, 2003

Filed:

Dec 21, 2001

Appl. No.:

10/026166

Inventors:

Xiaolin Wang - Concord MA, US
Satish Soman - Westboro MA, US
Benjamin Marshall - Stow MA, US
Subhasis Pal - Winchester MA, US

Assignee:

Axiowave Networks, Inc.

International Classification:

G06F012/00

US Classification:

711/220000

Abstract:

A sequential data packet addressing technique and system, particularly adapted for shared memory output-buffered switch fabrics and related memories, using a ring of successive subaddress generators each assigning addresses for predetermined size data byte packets received in successive time slots, and creating therefrom super packets ordered based on arrival time; and sequentially allocating memory therefor in the shared memory without overlap among the packets and with no holes between adjacent packets, and assigning addresses for the individual packets in the super packets upon the assigning of an address in the memory for each super packet.