Bernd Karl Appelt from Holly Springs, NC, age 76

Us Patents

Dustfree Prepreg And Method For Making An Article Based Thereon
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US Patent:

6387205, May 14, 2002
Filed:

Jan 24, 2000
Appl. No.:

09/489724
Inventors:

Bernd Karl Appelt - Apalachin NY
William Thomas Fotorny - Endicott NY
Robert Maynard Japp - Vestal NY
Kostantinos Papathomas - Endicott NY
Mark David Poliks - Vestal NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

B32B 3126
US Classification:

1563077, 1562726, 156182, 156315, 156329, 156330, 1563073, 427412, 4274073
Abstract:

A method for coating cloth especially fiberglass sheets with a thermosetting resin and resulting structure is provided. The coating is performed in two steps. In the first step, essentially all of the strands of the fiberglass are coated with the resin/solvent mixture while maintaining at least some of the interstices or openings essentially free of the solvent mixture. This first coating is then partially cured to between about 70% and 90% of full cure. The coated fiberglass with partially cured resin thereon is then given a second coating of either the same or different thermosetting resin mixture which coats the first coating and fills in the interstices between the fibers. This second coating is then partially cured, which advances the cure of the first coating past 80% full cure and results in an impregnated fiberglass cloth structure for use as sticker sheets. During lamination, the first coating acts like an impenetrable insulating sheet, preventing resin displacement and, therefore, preventing glass fiber contact with the conductive planes. The second coating is fluid enough to fill in spaces in the planes and to form the adhesive bond to cores and conductive layers.

Process For Manufacturing A Multi-Layer Circuit Board
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US Patent:

6391210, May 21, 2002
Filed:

Jul 9, 2001
Appl. No.:

09/901848
Inventors:

Bernd K. Appelt - Endicott NY
John M. Lauffer - Waverly NY
Voya R. Markovich - Endwell NY
Irving Memis - Vestal NY
David J. Russell - Apalachin NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01B 1300
US Classification:

216 13, 216 17, 264400, 264 401, 430311, 430314, 438 15, 438618, 21912171
Abstract:

A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.

Method For Preventing Adhesive Bleed Onto Surfaces
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US Patent:

6420253, Jul 16, 2002
Filed:

Jun 14, 2001
Appl. No.:

09/881466
Inventors:

Bernd K. Appelt - Brackney PA
Gary A. Johansson - Hockessin DE
Gerald W. Jones - Apalachin NY
Luis J. Matienzo - Endicott NY
Yenloan H. Nguyen - Binghamton NY
Konstantinos I. Papathomas - Endicott NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 2144
US Classification:

438612, 257784
Abstract:

A method and structure is provided for preventing wetting or bleed of an adhesive, such as an epoxy, onto noble metal wire bond pads on the surface of a dielectric substrate when attaching an I/C chip to the substrate. The method includes treating the wire bond pads with a chemical composition which prevents bleeding onto the surfaces of the wire bond pads by a component of the epoxy. The chemical composition is a chemical which will provide âSelf-Assembled Monolayersâ (SAMs) on the surface of the gold. These compositions are characterized by a molecule having at least one group, such as a mercaptan or disulfide, connected to a hydrocarbon moiety, such as a (CH ) chain. The affinity of the thiol or sulfur-containing portion of the molecule chemically bonding with the noble metal provides a relatively strong attachment of the molecule to the metal surface. The hydrocarbon segment presents a surface on the noble metal that has the characteristics of the hydrocarbon portion of the molecule which has a low surface tension, and, thus, prevents wetting of the noble metal by an epoxy adhesive component. The SAMs, once they provide protection from the bleed of the die attach adhesives, self desorb during the wire bonding or soldering temperatures.

Method For Producing Conductor Interconnect With Dendrites
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US Patent:

6427323, Aug 6, 2002
Filed:

May 17, 2001
Appl. No.:

09/859690
Inventors:

Bernd K. Appelt - Apalachin NY
Saswati Datta - Binghamton NY
Michael A. Gaynes - Vestal NY
John M. Lauffer - Waverly NY
James R. Wilcox - Vestal NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H05K 336
US Classification:

29830, 29852, 174250, 174262, 174266, 361313, 3613014, 361302
Abstract:

A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a âthrough via. â.

Chip Carriers With Enhanced Wire Bondability
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US Patent:

6534186, Mar 18, 2003
Filed:

Mar 27, 2001
Appl. No.:

09/818305
Inventors:

Konstantinos Papathomas - Endicott NY
Bernd Karl Appelt - Apalachin NY
John Joseph Konrad - Endicott NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

B32B 904
US Classification:

428447, 428421, 428422, 428461, 428901
Abstract:

A substrate that is substantially non-wettable to adhesive resin is disclosed. The substrate is coated with a fluorinated silane composition. Preferable fluorosilane compositions include perfluoroalkyl alkylsilanes of Formula III: wherein R is a perfluoroalkyl alkyl radical; R is alkyl or alkenyl; X is acetoxy, halogen or alkoxy; n is 1 or 2; and m is 0 or 1. The composition is preferably applied in solution and upon evaporation of the solvent, forms a durable, non-wetting, yet well-adhering surface. In a preferred embodiment, the substrate is a chip carrier with enhanced wire bondability for use in the manufacture of a semiconductor device.

Process For Filling Apertures In A Circuit Board Or Chip Carrier
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US Patent:

6534245, Mar 18, 2003
Filed:

Feb 21, 2001
Appl. No.:

09/788612
Inventors:

Bernd Karl Appelt - Endicott NY
Gary Alan Johansson - New Castle DE
Konstantinos I. Papathomas - Endicott NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G03F 700
US Classification:

430315, 430326, 430330, 427 97, 428209, 428901
Abstract:

Apertures in a circuit board or chip carrier are filled with a cured photosensitive dielectric material by substantially filling the apertures in the circuit board or chip carrier and applying a layer of a thickness to the circuit board or chip carrier with a positive photosensitive dielectric material, exposing the photosensitive dielectric material to actinic radiation in such a way as to leave material located in apertures unexposed to the radiation; baking the structure so as to harden the unexposed photosensitive dielectric material and developing the exposed dielectric material in order to remove it leaving behind cured photosensitive dielectric material in the apertures.

Electronic Package Having Substrate With Electrically Conductive Through Holes Filled With Polymer And Conductive Composition
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US Patent:

6555762, Apr 29, 2003
Filed:

Jul 1, 1999
Appl. No.:

09/345428
Inventors:

Bernd K. Appelt - Endicott NY
Jeffrey D. Gelorme - Plainville CT
Sung Kwon Kang - Chappaqua NY
Voya R. Markovich - Endwell NY
Kostas Papathomas - Endicott NY
Sampath Purushothaman - Yorktown Heights NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H05K 111
US Classification:

174264, 174257, 174258, 174265
Abstract:

The present invention provides a unique, high density, electronic package having a conductive composition for filling vias or through holes to make reliable vertical or Z-connects from a dielectric layer to adjacent electrical circuits. The through holes may be plated or non-plated prior to filling. A description for making high density electronic packaging using this feature is also disclosed.

Method Of Forming A Capacitive Element
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US Patent:

6625857, Sep 30, 2003
Filed:

Feb 1, 2001
Appl. No.:

09/773998
Inventors:

Bernd K. Appelt - Endicott NY
John M. Lauffer - Waverly NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01G 700
US Classification:

29 2542, 29 335, 295921, 29832, 29840, 3603014, 360323, 360312, 360761, 360762, 360763
Abstract:

A method of forming a capacitive element for a circuit board or chip carrier having improved capacitance is provided. The element is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The lamination takes place by laminating a partially cured sheet to at least one other sheet of dielectric material and one of the conductive sheets. The total thickness of the two sheets of the dielectric component does not exceed about 4 rolls and preferably does not exceed about 3 mils; thus, the single dielectric sheet does not exceed about 2 mils and preferably does not exceed about 1. 5 mils in thickness.